Frequency synthesizer using an arithmetic frequency synthesizer and plural phase locked loops

• US 4,516,084 A
• Filed: 02/18/1983
• Issued: 05/07/1985
• Est. Priority Date: 02/18/1983
• Status: Expired due to Fees

• Current Assignee: RCA Corporation
• Original Assignee: RCA Corporation
• Inventors: Crowley, Albert T.
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): Pascal, Robert J.
• Application Number:
  US06/467,644
• Time in Patent Office: 809 Days
• Field of Search: 331/2, 331/10, 331/11, 331/12, 331/16, 331/22, 331/25
• US Class Current: 331/2
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

A frequency synthesizer for controlling the frequency f₀ of a signal e₀ in response to a control signal e_c2 to produce a band of selectable frequencies separated by Δf between the frequencies f_x and f_y, where (f_x +RΔf)=f₀ and R is zero or any integer ≦(f_y -f_x)/Δf. The invention includes a first generator for generating the signal e₀, a second generator for generating a signal e₁ having a band of selectable frequencies separated by δf, where δf>>Δf, a frequency subtractor for subtracting f₁ from f₀ to produce a signal e₂ of frequency f₂. Also provided is a third generator for generating a variable preliminary reference signal of frequency f_pr consisting of a band of selectable frequencies separated by MΔf and lying within the frequency band Mf_x to Mf_y, where (Mf_x +R·MΔf)=Mf_r2 ; a divider for dividing Mf_r2 by M to produce a band of signal frequencies (f_x +RΔf)=f_r2 ; and a comparator for comparing f₂ with f_r2 to produce the control signal e_c2.

Claims

1. A frequency synthesizer comprising:

a phase locked loop comprising a first voltage controlled oscillator (VCO) for generating a signal e₁ of frequency f₁ and having a frequency control input, a divide-by-N divider to divide f₁ by N to produce a signal e_N of frequency f₁ /N, a first phase detector responsive to e_N and to a reference signal e_r1 of frequency f_r1 to produce a control signal e_c1, and means coupling e_c1 to the frequency control input of said first VCO;

a means for changing the value of N in said divider;

a summing phase locked loop comprising a second VCO for generating a signal e₀ of frequency f₀, and having a frequency control input, a subtractor for subtracting f₁ from f₀ to produce a signal e₂ of frequency f₂ =f₀ -f₁, logic means including a second phase detector responsive to e₂ and a second reference signal e_r2 to produce a second frequency control signal e_c2, and filter means responsive to e_c2 for supplying a filtered e_c2 '"'"' to the frequency control input of said second VCO; and

means for generating said second reference signal e_r2 comprising;

an accumulator containing digital data corresponding to the instantaneous phase of a waveform, said data contents being augmented by a selectable increment in response to each pulse of a clocking signal applied to said accumulator, said accumulator having overflow capability when said data contents are augmented beyond the capacity of said accumulator;

means responsive to said data contents of said accumulator for providing a signal of frequency f_AFS, said signal having said waveform and having period equal to the time between successive overflow occurrences of said accumulator;

source means for providing a heterodyning signal of predetermined frequency;

means responsive to said signal of frequency f_AFS and to said heterodyning signal for generating a heterodyned signal having frequency f_H which is the sum of f_AFS and the frequency of said heterodyning signal; and

means coupled to said heterodyned signal for dividing the frequency f_H of said heterodyned signal by an integer M to produce said second reference signal e_r2 of frequency f_r2.

2. A frequency synthesizer as in claim 1 in which said logic means further comprises voltage adder means responsive to the output signals of said first phase detector and said filter means to produce e_c2 '"'"'.

3. A frequency synthesizer as in claim 1 in which said means for generating said second reference signal further comprises a bandpass filter coupled between said means for generating a heterodyned signal and said dividing means.

4. A frequency synthesizer as in claim 1 in which said means for providing a signal of frequency f_AFS includes a read-only-memory (ROM) responsive at its addressing inputs to said data contents of said accumulator, said ROM containing digital amplitude data corresponding to the instantaneous phase of said waveform.

5. A frequency synthesizer as in claim 4 in which said means for providing a signal of frequency f_AFS further includes a digital-to-analog converter responsive at its inputs to said digital amplitude data of said ROM for providing said signal having said waveform.

6. A frequency synthesizer comprising:

a first divide-by-N phase locked loop comprising a÷

N counter, a first phase detector having first and second inputs, and a first voltage controlled oscillator (VCO), all connected in tandem, for generating a signal e₁ having frequency f₁, where f₁ =Nf_r1, with N being a variable integer and f_r1 being a first reference frequency supplied to said second input of said first phase detector;

a second VCO responsive to a control signal to generate an output signal e₀ of frequency f₀ ;

logic including subtracting means responsive to e₁ and e₀ to produce a signal e₂ of frequency f₂ =f₀ -f₁ ;

an accumulator containing digital data corresponding to the instantaneous phase of a waveform, said data contents being augmented by a selectable increment in response to each pulse of a clocking signal applied to said accumulator, said accumulator having overflow capability when said data contents are augmented beyond the capacity of said accumulator;

means responsive to said data contents of said accumulator for providing a signal of frequency f_AFS, said signal having said waveform and having period equal to the time between successive overflow occurrences of said accumulator;

source means for providing a heterodyning signal of predetermined frequency;

means responsive to said signal of frequency f_AFS and to said heterodyning signal for generating a heterodyned signal having frequency f_H which is the sum of f_AFS and the frequency of said heterodyning signal;

means coupled to said heterodyned signal for dividing the frequency f_H of said heterodyned signal by an integer M to produce a signal e_r2 of frequency f_r2, where f_r2 =f_H /M; and

a second phase detector responsive to e_r2 and e₂ to produce said control signal.

7. A method of synthesizing frequencies by altering the frequency f₀ of the output signal e₀ of a voltage controlled oscillator (VCO) in response to a control signal e_c2 comprising the steps of:

augmenting by a selectable increment and at a predetermined rate the data contents of a digital accumulator;

generating a signal e_AFS having waveform corresponding to said data contents, wherein said selectable increment determines the frequency f_AFS of said signal e_AFS, said frequency f_AFS being selectable within a first band of frequencies separated by MΔ

f, where M is a positive integer;

combining signal e_AFS with a heterodyning signal of predetermined frequency F_H to produce a preliminary reference signal having frequency within a second band of frequencies which is the sum of F_H and said first band of frequencies;

dividing the frequency of said preliminary reference signal by M to produce a second reference signal e_r2 having frequency within a third band of selectable frequencies separated by Δ

f;

generating a signal e₁ having a frequency f₁ which is variable in steps of δ

f₁, where δ

f₁ >

>

Δ

f;

subtracting f₁ from f₀ to produce a signal e₂ of frequency f₂ ; and

comparing the frequency and phase of e_r2 and e₂ to produce the control signal e_c2.

8. A method of synthesizing frequencies by altering the frequency f₀ of the output of a voltage controlled oscillator (VCO) in response to a control signal e_c2 comprising the steps of:

generating a first signal e₁ having a frequency f₁ which is alterable in steps of δ

f;

producing a second signal e₂ of frequency f₂ where f₂ =(f₀ -f₁);

augmenting by a selectable increment and at a predetermined rate the data contents of a digital accumulator;

generating a signal e_AFS having waveform corresponding to said data contents, wherein said selectable increment determines the frequency f_AFS of said signal e_AFS, said frequency f_AFS being selectable within a first band of frequencies separated by MΔ

f, where M is an integer;

combining signal e_AFS with a heterodyning signal of predetermined frequency F_H to produce a preliminary reference signal having frequency Mf_r2 within a second band of frequencies which is the sum of F_H and said first band of frequencies;

dividing the frequency of said preliminary reference signal by M to produce a second reference signal e_r2 having frequency f_r2 within a third selectable band of frequencies spaced apart by Δ

f; and

comparing f₂ with f_r2 to produce e_c2.

9. A frequency synthesizer for controlling the frequency f₀ of a signal e₀ in response to a control signal e_c2 to produce a band of selectable frequencies separated by Δ

f between the frequencies f_x and f_y, where (f_x +MΔ

f)=f₀ and M is zero or any positive integer≦

(f_y -f_x)/Δ

f, said frequency synthesizer comprising;

first means for generating a signal e₀ having frequency f₀ ;

second means for generating a signal e₁ having a band of selectable frequencies f₁ separated by δ

f, where δ

f>

>

Δ

f;

means for subtracting f₁ from f₀ to produce a signal e₂ of frequency f₂ =f₀ -f₁ ;

a digital accumulator responsive to pulses of a clocking signal of a predetermined frequency, wherein the data contents of said digital accumulator are augmented by a selectable increment;

third means for generating a signal e_AFS corresponding to said data contents of said digital accumulator, wherein said selectable increment determines the frequency f_AFS of said signal e_AFS, said frequency f_AFS being selectable within a first band of frequencies separated by MΔ

f;

source means for providing a heterodyning signal of predetermined frequency F_H ;

means for combining signal e_AFS with said heterodyning signal to produce a variable preliminary reference signal of frequency Mf_r2 =f_AFS +F_H, wherein Mf_r2 lies within a second band of frequencies which is the sum of F_H and said first band of frequencies;

means for dividing the frequency of said preliminary reference signal by M to produce a signal of frequency f_r2 within a band of frequencies f_x to f_y ; and

means for comparing f₂ with f_r2 to produce the control signal e_c2.