Memory system with single command selective sequential accessing of predetermined pluralities of data locations

• US 4,516,218 A
• Filed: 06/26/1980
• Issued: 05/07/1985
• Est. Priority Date: 06/26/1980
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hamilton, Stephen P.
• Primary Examiner(s): Thomas, James D.
• Assistant Examiner(s): WILLIAMS JR, ARCHIE E
• Application Number:
  US06/163,025
• Time in Patent Office: 1,776 Days
• Field of Search: 364/200, 364/900, 364/706, 364/708
• US Class Current: 711/200
• CPC Class Codes: G06F 1/00 Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 architectures of general purpose stored program computers G06F15/76
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

This addressing system, advantageously for smaller scale data processors with relatively narrow data paths, facilitates transferring pluralities of multibit data words, e.g., storing or fetching the contents of a multidigit register in a calculator. A bidirectional bus couples a controller and a plug-in memory. The controller generates address, data, and command signals. A decoder receives command signals and outputs signals to a program counter (PC) alternatively indicating a normal mode, in which the controller accesses a single specified memory address, or a multiple access mode, in which a predetermined number of sequential addresses are accessed starting at a specified address. In response to selective command decoder output, the PC alternatively may store received addresses, output stored count values to the controller or to a memory array, or increment the count value in synchronism with data transfers to/from multiple memory locations. The decoder, PC, and memory array are contained within the portable memory module'"'"'s housing, which may be mounted in another housing containing the controller.

In a ROM embodiment, the mounted memory is powered directly from a source in the controller housing. In a RAM embodiment, the module'"'"'s housing includes a power switching circuit and an internal battery to provide uninterrupted power to the read/write memory cells irrespective of whether the module is mounted or detached.

Claims

1. A memory system comprising:

a bidirectional bus means coupled to a source for providing command signals, address signals and data signals;

a command decode means coupled to said bus means for generating respective first, second and at least a third decode outputs in response to receipt of first, second and at least a third command signals;

a program counter means coupled to said bus means and to said command decode means for storing therein an address corresponding to an address signal received via said bus means upon receipt of said first decode output, for generating an address signal corresponding to said address stored therein upon receipt of said second decode output, and for sequentially and repetitively generating an address signal corresponding to said address stored therein and incrementing said address stored therein upon receipt of said third decode output, this sequential and repetitive operation being repeated a predetermined number of times corresponding to said third command signal; and

a memory array coupled to said bus means, said command decode means and said program counter means, having a plurality of multibit data words stored at memory locations therein corresponding to said address signals, for providing multibit data words as data signals to said bus means upon receipt of said address signals from said program counter means in response to either said second decode output or said third decode output from said command decode means.

2. A memory system as claimed in claim 1, wherein:

said third command signal is a multiple memory location recall command signal; and

said memory means produces data signals corresponding to multibit data words stored at memory locations corresponding to said address signals received from said program counter means and applies said data signals to said bus means.

3. A memory system as claimed in claim 1, wherein:

said third command signal is a multiple memory location store signal; and

said memory array receives data signals from said bus means and stores multibit data signals corresponding to said received data signals at memory locations corresponding to said address signals received from said program counter means.

4. A memory system as claimed in claim 1, further comprising:

memory module housing means having said bus means, said command decode means, said program counter means and said memory array disposed therein, said memory module housing means having connector means connected to said bus means for removable connection to a data processing apparatus.

5. A data processing apparatus comprising:

a controller means for generating command signals, address signals and data signals, said command signals comprising a load address command signal, a single memory location command signal corresponding to memory transfer operation utilizing a single memory location, and at least one multiple memory location command signal corresponding to a memory transfer operation utilizing a predetermined number of memory locations;

a bidirectional bus means coupled to said controller for transmitting said command signals, address signals and data signals;

a command decode means coupled to said bus means for generating respective first, second and at least a third decode output in response to receipt of said load address command signal, said single memory location command signal and said at least one multiple memory location command signal, respectively;

a program counter means coupled to said bus means and to said command decode means for storing therein an address corresponding to an address signal received via said bus means upon receipt of said first decode output, for generating an address signal corresponding to said address stored therein upon receipt of said second decode output, and for sequentially and repetitively generating an address signal corresponding to said address stored therein and incrementing said address stored therein upon receipt of said third decode output, this sequential and repetitive operation being repeated a predetermined number of times corresponding to said multiple memory location command signal; and

a memory array connected to said bus means, said command decode means and said program counter means having a plurality of multibit data words stored at memory locations therein corresponding to said address signals, for providing multibit data words as data signals to said bus means upon receipt of said address signals from said program counter means in response to either said second decode output or said third decode output from said command decode means.

6. A data processing system according to claim 5 wherein said memory array is a read only memory.

7. A data processing system according to claim 5 wherein said memory array is a read/write memory.

8. A data processing apparatus as claimed in claim 5, wherein:

said at least one multiple memory location command signal includes a multiple memory location store command signal.

9. A data processing apparatus as claimed in claim 5 wherein:

said at least one multiple memory location command signal includes a multiple memory location recall command signal.

10. A data processing apparatus as claimed in claim 5 wherein:

said memory means further includes a memory controller means for generating an active enable output and an inactive enable output; and

said command decode means includes means connected to said memory controller means for enabling generation of decode outputs in response to received command signals only when said memory controller means is generating said active enable output.

11. A data processing apparatus as claimed in claim 5 wherein:

said command signals generated by said controller means further includes an address read command signal;

said command decode means includes means for generating a fourth decode output in response to said address read command signal; and

said program counter means includes means for generating an address signal corresponding to said address stored therein upon receipt of said fourth decode output and applying said address signal to said bus means.