Unified CMOS/SNOS semiconductor fabrication process

• US 4,516,313 A
• Filed: 05/27/1983
• Issued: 05/14/1985
• Est. Priority Date: 05/27/1983
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: Turi, Raymond A., Pfeifer, Robert F.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Schiavelli, Alan E.
• Application Number:
  US06/499,044
• Time in Patent Office: 718 Days
• Field of Search: 148/1.5, 148/187, 29/571, 29/577 C, 29/591, 357/23 VT, 357/41, 357/42
• US Class Current: 438/200
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions

Abstract

A unified process for fabricating CMOS and SNOS devices on a common wafer. The process provides for the formation of poly resistors and interconnects at multiple levels while eliminating residual silicon nitride from active devices excepting the nonvolatile SNOS type memory cells. Foremost, the process significantly reduces the number of masking operations while limiting the fabrication temperatures at stages after the formation of the memory device dielectric. In the preferred arrangement, the process prescribes the formation of p and n-wells, gate oxides over the wells, and a patterned conductive poly layer thereupon. By alternate photoresist masking, the source/drain regions in the respective wells are then doped to coincide with the corresponding poly layer patterns. Thereafter, the SNOS device operational characteristics are refined, a first isolation layer of silicon dioxide is grown, and the memory dielectric is sequentially formed. Following the deposition of another conductive poly layer, this layer and the underlying silicon nitride from the memory dielectric are together selectively etched to retain the second layer of poly only at interconnect locations, resistors and the SNOS devices. Fabrication is concluded with the formation of a second isolation oxide and a patterned layer of interconnect metal.

Claims

1. A unified process for fabricating CMOS and SNOS type devices on a semiconductor substrate, comprising the steps of:

forming wells of first and second impurity type in a common semiconductor substrate;

forming field oxides between the wells;

forming gate oxide layers over the wells;

forming a first patterned conductive layer over the field oxides and gate oxide layers as gate and interconnect electrodes;

selectively doping regions in the first and second impurtiy type wells to form interconnect and S/D regions selectively self-aligned with the first patterned conductive layer and of an impurity type opposite that of the respective well;

lightly doping the substrate at the SNOS device with a impurity type opposite that of the SNOS device well;

forming a first isolation oxide layer over the first patterned conductive layer and the selectively doped regions;

selectively removing oxide from over the SNOS device to expose the semiconductor substrate;

forming a memory dielectric over the exposed semiconductor substrate;

selectively removing memory dielectric and oxide from the selectively doped regions in the first and second impurity type wells;

forming a second patterned conductive layer over the semiconductor substrate;

forming a second isolation dielectric layer over the second patterned conductive layer; and

forming conductive contacts to selectively interconnect the doped interconnect regions, the S/D regions, the first patterned conductive layer and the second patterned conductive layer.

2. The process recited in claim 1, wherein said step of forming a first patterned conductive layer is comprised of:

depositing a first poly layer;

heavily doping the first poly layer with first impurity type dopant; and

selectively etching the doped first poly layer.

3. The process recited in claim 2, wherein said step of forming a first isolation oxide layer is comprised of growing oxides from the semiconductor substrate and the first poly layer.

4. The process recited in claim 3, wherein said steps of forming a memory dielectric and selectively removing memory dielectric and oxide are comprised of:

growing a very thin oxide layer;

forming a nitride-based dielectric layer; and

selectively etching the nitride-based dielectric layer and any oxide layers to selectively expose interconnect and S/D regions.

5. The process recited in claim 4, wherein said step of forming a second patterned conductive layer is comprised of:

depositing a second poly layer;

resistively doping the second poly layer with first impurity type dopant;

selectively etching the second poly layer; and

heavily doping selected regions of the second poly layer.

6. The process recited in claim 5, including the step of selectively implanting the SNOS device to center the memory window performed before said step of selectively removing oxide from over the SNOS device.

11. The process recited in claim 5, wherein said steps beginning with forming a second patterned conductive layer and concluding with doping the exposed regions are comprised of:

depositing a second poly layer;

selectively etching the second poly layer to retain regions over the SNOS devices and resistively doped regions of the first poly layer;

selectively etching the nitride-based dielectric layer, the very thin oxide layer, and the oxide grown at a differential rate, to expose the heavily doped regions in the first poly layer; and

heavily doping exposed regions of the first and second poly layers with first impurity type dopant.

12. The process recited in claim 11, including the step of selectively implanting the SNOS devices to center the memory window, performed before said step of selectively removing oxide from over the SNOS devices.

13. The process recited in claim 6, wherein said step of forming conductive contacts is comprised of:

etching contact cuts through the isolation dielectric layer and the oxide layers to selectively expose doped interconnect regions, S/D regions, in poly layers;

forming barrier metal contacts to the exposed poly layers and semiconductor substrate regions; and

forming selectively patterned metallic interconnects.

14. The process recited in claim 12, wherein said step of forming conductive contacts is comprised of:

etching contact cuts through the isolation dielectric layer and the oxide layers to selectively expose doped interconnect regions, S/D regions, in poly layers;

forming barrier metal contacts with the exposed poly layers and semiconductor substrate regions; and

forming selectively patterned metallic interconnects.

7. A unified process for fabricating CMOS and SNOS type devices on a common semiconductor substrate, comprising the steps of:

forming wells of first and second impurity type in a common semiconductor substrate;

forming field oxides between the wells;

forming gate oxide layers over the wells;

selectively removing oxide from over the second impurity type wells;

forming a first patterned conductive layer over the field oxides and gate oxides layers as gate and interconnect electrodes;

selectively doping interconnect and S/D regions, to selectively self-align with the first patterned conductive layer, in the second impurity type wells, and selected regions in the first patterned conductive layer, using first impurity type dopant;

selectively doping interconnect and S/D regions, to selectively self-align with the first pattern conductive layer, in the first impurity type wells using second impurity type dopant;

lightly doping the substrate at the SNOS device with an impurity type opposite of that of the SNOS device well;

forming a first isolation oxide layer, so that the thickness of the oxide over the first patterned conductive layer is significantly less than the thickness of the oxide over the remaining semiconductor substrates;

selectively removing oxide from over the SNOS device to expose the semiconductor substrate;

forming a memory dielectric over the exposed semiconductor substrate;

forming a second patterned conductive layer over the semiconductor substrate;

selectively removing memory dielectric using the second patterned conductive layer as a mask;

removing the first isolation oxide until the first patterned conductive layer, not masked by the second patterned conductive layer, is exposed;

doping the exposed regions of the first and second patterned conductive layers with first impurity type dopant;

forming an isolation dielectric layer over the semiconductor substrate; and

forming conductive contacts to selectively interconnect the doped interconnect regions, the S/D regions, the first patterned conductive layer, and the second patterned conductive layer.

8. The process recited in claim 7, wherein said steps of forming a first patterned conductive layer and selectively doping interconnect and S/D regions in the second impurity type wells are comprised of:

depositing a first poly layer;

resistively doping the first poly layer with first impurity type dopant;

selectively etching the first poly layer; and

heavily doping selected interconnect and S/D regions in the second impurity type wells, and selected regions in the first poly layer, with first impurity type dopant.

9. The process recited in claim 8, wherein said step of forming the first isolation oxide layer is comprised of:

growing oxide from the first poly layer and the semiconductor substrate at an accentuated differential rate until the thickness of the oxide over the substrate is at least 400 Angstroms greater than the thickness of the oxide over the first poly layer.

10. The process recited in claim 9 wherein said step of forming a memory dielectric layer is comprised of:

growing a very thin oxide layer; and

forming a nitride-based dielectric layer.