Interference recognition circuit in a heart pacemaker

• US 4,516,579 A
• Filed: 08/26/1983
• Issued: 05/14/1985
• Est. Priority Date: 09/01/1982
• Status: Expired due to Term

• Current Assignee: Werner Irnich
• Original Assignee: Werner Irnich
• Inventors: Irnich, Werner
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/527,177
• Time in Patent Office: 627 Days
• Field of Search: 128/419 PG, 128/696-698, 128/708
• US Class Current: 607/9
• CPC Class Codes: A61N 1/365 controlled by a physiological parameter, e.g. heart potential evoked response A61N1/371
• CPC Class Codes: A61N 1/3704 Circuits specially adapted therefor, e.g. for sensitivity control

Abstract

A synchronizable heart pacemaker includes a timing circuit, a differentiating circuit for receiving signals, and an interference recognition circuit connected to the output of the differentiating circuit. The interference recognition circuit includes a testing stage for each signal. An output signal normally appears on an output of the testing stage, and the testing stage includes a peak detector circuit which stores a positive maximum value and a negative maximum value of each signal differentiated by the differentiating stage, and an adder forming the sum of said maximum values. A discriminator stage is postcoupled to the testing stage. The discriminator stage generates a time interval corresponding approximately to a time duration of the QRS-complex of a heart-action signal, and includes a checking circuit for checking the presence or absence of the output signal of the testing stage after said time interval, and a decision circuit for recognizing the output signal either as an interfering signal, and thereafter rendering the interfering signal ineffective, or recognizing the output signal as the heart-action signal, and passing the heart-action signal to the timing circuit.

Claims

1. A synchronizable heart pacemaker

comprising in combination

a timing circuit for generating a stimulating impulse after an expected time interval,

differentiating means for receiving signals,

interference recognition means connected to the output of said differentiating means, and including

a testing stage for each signal, an output signal normally appearing on an output of said testing stage, said testing stage including a peak detector circuit storing a positive maximum value and a negative maximum value of each signal differentiated by an adder which further acts as an amplifier and which forms the difference of both positive and negative maximum values, and a comparator postcoupled with one input thereof to said adder and with another input thereof to a reference voltage,

a discriminator postcoupled to the testing stage, said discriminator stage generating a time interval corresponding approximately to a time duration of the QRS complex of a heart-action signal, and including

checking means for checking for the presence or absence of said output signal after said time interval, and

decision means for recognizing said output signal in the presence thereof within said time interval either as an interfering signal, and thereafter rendering said interfering signal ineffective, or recognizing said output signal as said heart-action signal and passing said heart-action signal to said timing circuit.

2. The heart pacemaker as claimed in claim 1, wherein said differentiating means comprises a capacitor and a resistor connected with one end thereof in series with said capacitor, and with the other end thereof to ground possessing an upper frequency limit of 1 kHz.

3. The heart pacemeaker as claimed in claim 2, wherein said testing stage includes a first storage capacitor and a first diode connected in series therewith for storing said positive maximum value, and a second storage capacitor, and a second diode connected in series with said second storage capacitor for storing said negative maximum value, as well as an operational amplifier, and first and second resistors connecting said first and second capacitors, respectively, to said operational amplifier.

4. The heart pacemaker as claimed in claim 3, wherein said discriminator stage includes a monostable multivibrator having a predetermined switch-over time, said capacitors being dischargeable to a definite value within said switch-over time.

5. A synchronizable heart pacemaker for generating a current impulse after an expected time interval, said expected time interval being normally started by a heart-action signal, said heart-action signal including a QRS complex appearing within a predetermined time interval, starting with a positive-going spike, followed by a negative-going spike of a predetermined absolute magnitude and steepness followed by a positive-going spike of reduced steepness, followed in turn by a relatively broad excursion of a smaller absolute steepness than said predetermined absolute steepness, said broad excursion having a relatively low-frequency content, each of said spikes having a relatively high-frequency content,

comprising in combination

a timing circuit for generating said current impulse after said expected time interval,

differentiating means for receiving signals,

interference recognition means connected to the output of said differentiating means, and including a testing stage for each signal, an output signal normally appearing on an output of said testing stage

a discriminator stage postcoupled to the testing stage, said discriminator stage including

decision means for checking the presence or absence of said output signal within said expected time interval, and heart action signal recognition means for recognizing said output signal either as an interfering signal, and thereafter rendering said interfering signal ineffective, or recognizing said output signal as said heart-action signal and passing said heart-action signal to said timing circuit in the event of the presence of said output signal within said time interval, said timing circuit being adapted to only cause generation of a current impulse passed to a stimulation electrode for stimulating the failing heart of a patient, provided no other heart-action signal occurs within said expected time interval.

6. The heart pacemaker as claimed in claim 5, wherein said discriminator stage includes a delay circuit generating a time interval corresponding to the duration of the QRS-complex, a refractory circuit postcoupled to said delay circuit generating a perceptibility pause of Q-T-duration, and a coincidence circuit postcoupled to said refractory circuit with one input thereof, and connected with another input thereof to the output of said testing stage.

7. The heart pacemaker as claimed in claim 5, wherein said delay circuit includes a first monostable multivibrator, and said refractory circuit includes a second monostable multivibrator, having a reset input enabled upon said recognition means recognizing said interference signals.

8. The heart pacemaker as claimed in claim 5, wherein said peak-value storage means includes first and second capacitors, first and second transistors connected of respective opposite polarities as emitter followers for charging said first and second capacitors, and third and fourth transistors connected as emitter followers at polarities opposite to that of said first and second transistors for feeding said stored voltages to said decision means.

9. The heart pacemaker as claimed in claim 5, wherein said peak-value storage means include first and second capacitors chargeable to respective positive and negative voltages, and further comprising first discharge means for discharging said capacitors at a slow rate, and second discharge means for discharging said capacitors at a much faster rate than said slow rate.

10. The heart pacemaker as claimed in claim 5, wherein said heart-action signal recognition means further includes steepness recognition means for recognizing said output signal as a heart-action signal only upon said negative-going spike exceeding a predetermined steepness.

11. A synchronizable heart pacemaker for generating a current impulse after an expected time interval, said expected time interval being normally started by a heart-action signal, said heart-action signal including a QRS complex appearing within a predetermined time interval, starting with an initial positive-going spike, followed by a negative-going spike of a predetermined absolute magnitude and steepness, followed by a positive-going spike of reduced steepness, followed in turn by a relatively broad excursion of a smaller absolute steepness than said predetermined absolute steepness, said broad excursion having a relatively low-frequency content, each of said spikes having a relatively high-frequency content,

comprising in combination

a timing circuit for generating said current impulse after said expected time interval,

differentiating means for receiving signals, each differentiated signal having a positive peak value, and a negative peak value,

a testing stage connected to the output of said differentiating means, and including a preamplifier, peak-value storage means postcoupled to said preamplifier for storing said positive and said negative values of each signal differentiated by said differentiating means, and a signal conditioner including an adder postcoupled to said peak-value storage means, an output signal normally appearing on an output of said testing stage,

said adder forming a sum from said positive and negative values, and

a discriminator stage postcoupled to the testing stage, said discriminator stage including

heart-action signal recognition means, including

polarity-sensing means for sensing the polarity of said sum formed by said adder, and passing said output signal to said timing circuit only when said sum is negative and exceeds a predetermined absolute value,

interference recognition means for recognizing any non-recurring signal having a predominantly positive rise time, and substantially any periodic pulsed or amplitude-modulated signals as interference signals, and

interference suppression means for preventing said interference signals from being passed to said timing circuit,

said timing circuit being adapted to only cause generation of a current impulse passed to a stimulation electrode for stimulating the failing heart of a patient, provided no other heart-action signal occurs within said expected time duration.

12. The heart pacemaker as claimed in claim 11, wherein said discriminator stage includes a delay circuit generating a time interval corresponding to the duration of the QRS-complex, a refractory circuit postcoupled to said delay circuit generating a perceptibility pause of Q-T-duration, and a coincidence circuit postcoupled to said refractory circuit with one input thereof, and connected with another input thereof to the output of said testing stage.

13. The heart pacemaker as claimed in claim 11 wherein said delay circuit includes a first monostable multivibrator, and said refractory circuit includes a second monostable multivibrator, having a reset input enabled upon said interference recognition means recognizing said interference signals.

14. The heart pacemaker as claimed in claim 11, wherein said peak-value storage means includes first and second capacitors, first and second transistors connected of respective opposite polarities as emitter followers for charging said first and second capacitors, and third and fourth transistors connected as emitter followers at polarities opposite from said first and second transistors for feeding said stored voltages to said signal conditioner.

15. The heart pacemaker as claimed in claim 11, wherein said peak-value storage means include first and second capacitors chargeable to respective positive and negative voltages, and further comprising first discharge means for discharging said capacitors at a slow rate, and second discharge means for discharging said capacitors at a much faster rate than said slow rate.

16. The heart pacemaker as claimed in claim 15, wherein said first discharge means includes a resistor.

17. The heart pacemaker as claimed in claim 15, wherein said second discharge means includes an analog switch.

18. The heart pacemaker as claimed in claim 15, wherein said second discharge means includes field effect transistors.

19. The heart pacemaker as claimed in claim 11, wherein said heart-action signal recognition means further includes steepness recognition means for recognizing said output signal as a heart-action signal only upon said negative-going spike exceeding a predetermined steepness.

20. The heart pacemaker as claimed in claim 11, wherein said discriminator stage includes a monostable multivibrator having a predetermined switch-over time, said capacitors being dischargeable to a difinite value within said switch-over time.