FSK Demodulator employing a switched capacitor filter and period counters

• US 4,517,519 A
• Filed: 11/05/1981
• Issued: 05/14/1985
• Est. Priority Date: 11/07/1980
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Suwa Seikosha
• Original Assignee: Kabushiki Kaisha Suwa Seikosha
• Inventors: Mukaiyama, Fumiaki
• Primary Examiner(s): LaRoche, Eugene R.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/318,496
• Time in Patent Office: 1,286 Days
• Field of Search: 329/50, 329/107, 329/110, 329/126, 375/45, 375/47, 375/48, 375/88, 375/89, 375/90, 375/94, 375/95, 375/96, 375/103, 375/104
• US Class Current: 329/303
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H04L 27/1563 using transition or level detection

Abstract

An FSK demodulation circuit especially suited for integrated construction is provided. The demodulating circuit uses N counters and a counter selector circuit for sequentially switching the counters at every zero-cross point in the received FSK signal. Sensitivity of demodulation is improved by N-time zero-cross detection rather than counting the time between two adjacent zero-cross points. The FSK demodulation circuit uses a Switched Capacitor Bandpass Filter whose characteristics are changed by changing the frequency of an internal clock using simple dividing circuitry.

Claims

1. In an FSK demodulation circuit including a zero-cross detection circuit to demodulate a received binary signal, said binary signal being produced by frequency shift keying techniques whereby marks and spaces are transmitted at different selected frequencies, the improvement comprising:

a signal period counter, said signal period counter including a plurality N of counter sections;

a counter section selector circuit, said selector circuit selecting said counter sections in sequence for reading out a count at every detected zero-cross of said received binary signal, said selector circuit selecting said counter sections in sequence for resetting each of said counter sections, counting pulses from a clock and holding the count accumulated in each of said counter sections between said resetting and said reading out, said count being detected to determine whether said received frequency signal represents one of a mark and a space, said counting period for each of said counter sections equalling N zero-cross detection periods,

whereby the signal-to-noise ratio of said demodulation circuit is enhanced by an increase in the number of accumulated counts by a factor of N, relative to a substantially unvarying noise input.

2. A FSK demodulation circuit as claimed in claim 1, and further comprising a clock signal generator, the output of said clock generator being applied to each of said counter sections.

3. An FSK demodulation circuit for receiving and demodulating an analog signal, said analog signal being modulated in response to a binary signal, said analog comprising one of an originate pair of analog frequencies respectively corresponding to a binary "1" and a binary "0" and an answer pair of analog frequencies respectively corresponding to a binary "1" and a binary "0", said answer pair of analog frequencies being distinct from said originate pair of analog frequencies, the demodulation circuit comprising:

clock means for generating a clock signal having one of a first clock frequency and a second clock frequency;

switched capacitor band pass filter means having said analog and said clock signal as inputs, said switched capacitor band pass filter means passing said originate pair of analog frequencies when said clock signal is at said first clock frequency, said switched capacitor band pass filter means passing said answer pair of analog frequencies when said clock signal is at said second clock frequency;

means coupled to said clock means for selecting one of the clock signals to be generated;

period counter means, said period counter means comprising N counter sections; and

counter section selector means, said selector means selecting said counter sections in sequence to read out a count at every detected zero-cross of said analog signal, said counter section selector means selecting said counter sections in sequence for resetting, counting pulses from a clock, and holding the count which is accumulated in each of said counter sections between said resetting and said reading out, said count being detected to determine whether said binary signal represents a binary "1" or a binary "0", said counting period for each of said counter sections equalling N zero-cross detection periods.

4. An FSK demodulation circuit, as claimed in claim 3, and including switching means for switching said clock signal between said first clock frequency and said second clock frequency.

5. An FSK demodulation circuit, as claimed in claim 4, wherein said frequency of said clock signal is selected to be several tens times the frequency of said analog signal.

6. An FSK demodulation circuit for receiving and demodulating first and second analog signals which are modulated in response to a binary signal, said first analog signal comprising one of a first pair of analog frequencies respectively corresponding to a binary "1" and a binary "0" and a second pair of analog frequencies respectively corresponding to a binary "1" and binary "0", said second pair of analog frequencies being distinct from said first pair of analog frequencies, said second analog signal comprising a third pair of analog frequencies respectively corresponding to a binary "1" and a binary "0" and a fourth pair of analog frequencies respectively corresponding to binary "1" and a binary "0", said third and fourth pairs of analog frequencies being distinct from each other and from said first and second pair of analog frequencies, the demodulation circuit comprising:

clock means for generating a clock signal having one of a first clock signal and a second clock signal as an output, said first clock signal comprising one of a first clock frequency and a second clock frequency and said second clock signal comprising one of a third clock frequency and a fourth clock frequency;

first switched capacitor band pass filter means having said analog signal and said clock signal as inputs, said first switched capacitor band pass filter means passing said first pair of analog frequencies when said clock signal is at said first clock frequency and said first switched capacitor band pass filter means passing said second pair of analog frequencies when said clock signal is at said second clock frequency;

second switched capacitor band pass filter means having said analog signal and said clock signal as inputs, said second switched capacitor band pass filter means passing said third pair of analog frequencies when said clock signal is at said third clock frequency and said second switched capacitor band pass filter means passing said fourth pair of analog frequencies when said clock signal is at said fourth clock frequency;

means coupled to said clock means for selecting one of the clock signals to be generated;

period counter means, said period counter means comprising N counter sections; and

counter section selector means, said selector means selecting said counter sections in sequence to read out a count at every detected zero-cross of said analog signal, said counter section selector selecting said counter sections in sequence for resetting, counting pulses from a clock, and holding the count which is accumulated in each of said counter sections between said resetting and said reading out, said count being detected to determine whether said received binary signal represents a binary "1" or a binary "0", said counting period for each of said counter sections equalling N zero-cross detection periods.

7. An FSK demodulation circuit in accordance with claim 6 wherein the values of the four clock frequencies are a set of four clock frequencies respectively corresponding to a CCITT originate pair, to one of a CCITT originator pair and a CCITT answer pair, and a Bell originate pair and a Bell answer pair.