Radar trigger and pretrigger generator having delay sensing and compensating circuit

• US 4,517,567 A
• Filed: 02/25/1982
• Issued: 05/14/1985
• Est. Priority Date: 02/25/1982
• Status: Expired due to Term

• Current Assignee: Sp-Marine Incorporated
• Original Assignee: Sperry Corporation
• Inventors: Bean, Donald E., Jones, Randy T., Lee, Patrick G.
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Glenny, Raymond C.
• Application Number:
  US06/352,484
• Time in Patent Office: 1,174 Days
• Field of Search: 332/5, 331/5, 331/87, 375/71, 375/23, 343/17.1 R, 343/17.7, 343/5 SW, 343/5 ST, 343/5 SM, 307/234, 307/269, 328/63
• US Class Current: 342/202
• CPC Class Codes: G01S 7/282 Transmitters

Abstract

The radar trigger and pretrigger generator determines the inherent component time delay through the radar modulator and transmitter during a first cycle of operation. During the next cycle of operation a pretrigger pulse is generated after a time corresponding to the previously measured delay and a trigger pulse is generated after a time corresponding to an operator selectable delay. The trigger pulse is used to trigger the radar modulator, which in effect, permits the operator to control the elapsed time between pretrigger pulse and transmitter firing in a fashion which is completely independent of circuit delay variances through the radar modulator and transmitter.

Claims

1. An apparatus for providing a trigger pulse to a circuit and a pretrigger pulse with a preselected time delay between the pretrigger pulse and the responsive signal output from the circuit comprising:

means for providing reference pulses,

means coupled to trigger input means of said circuit and responsive to said reference pulses for generating said trigger pulses after a preselected time delay from said reference pulses,

means coupled to said trigger input means to receive said trigger pulses and to output means of said circuit to receive output signals therefrom for measuring time delays between said trigger pulses and said output signals and for providing signals representative of said measured time delays, and

means coupled to receive said time delay representative signals and said reference pulses for providing pretrigger pulses at a time after receipt of said reference pulses that is equal to said measured time delay.

2. An apparatus according to claim 1 wherein said time delay measuring means comprises:

delay counter means coupled to receive clock pulses, for producing clock counts representative of said time delays between said trigger pulses and said output signals; and

first bistable means coupled to said delay counter means, to said trigger pulse means for enabling said delay counter means in response to trigger pulses, and to said output means for disabling said delay counter means in response to said output signals.

3. The apparatus according to claim 2 wherein said time delay measuring means further includes second bistable means responsive to said reference pulse for enabling said pretrigger pulse means and responsive to said pretrigger pulse for disabling said pretrigger pulse means.

4. The apparatus according to claim 1 wherein said trigger pulse generator means includes means coupled to receive said reference pulses and clock pulses for providing trigger pulses at said preselected times after said reference pules.

5. The apparatus according to claim 4 wherein said trigger pulse generator means further includes a counter having output means coupled to said circuit and a third bistable means coupled to said counter, said third bistable means responsive to said reference pules for enabling said counter and responsive to said trigger pulses for disabling said counter.

6. The apparatus according to claim 5 wherein said trigger pulse generator means further comprises means coupled to said counter for establishing a count representative of said preselected time delay.

7. Apparatus for triggering a modulator of a RF transmitter to emit transmitter trigger pulses and for providing pretrigger pulses at preselected times therebefore comprising:

means for providing reference pulses,

means coupled to trigger input means of said modulator and responsive to said reference pules for providing trigger pulses to said modulator after a preselected time delay from said reference pulses,

means coupled to said trigger input means to receive said trigger pulses and to output means of said modulator to receive said transmitter trigger pulses for measuring time delays between said trigger pulses and said transmitter trigger pulses and for providing signals representative thereof, and

means responsive to said time delay representative signals and said reference pulses for generating pretrigger pulses at a time after receipt of said reference pulses that is equal to said measured time delay.

8. An apparatus according to claim 7 wherein said time delay measuring mean comprises:

delay counter means coupled to receive clock pulses, for producing clock counts representative of said time delays between said trigger pulses and transmitter trigger pulses; and

first bistable means coupled to said delay counter means, to said trigger pulse means for enabling said delay counter means in response to trigger pulses and to said output means of said modulator for disabling said delay counter means in response to said transmitter trigger pulses.

9. The apparatus according to claim 8 wherein said time delay measuring means further includes second bistable means responsive to said reference pulse for enabling said pretrigger pulse means and responsive to said pretrigger pulse for disabling said pretrigger pulse means.

10. The apparatus according to claim 7 wherein said trigger pulse generator means includes means coupled to receive said reference pulses and clock pulses for providing trigger pulses at said preselected times after said reference pulses.

11. The apparatus according to claim 10 wherein said trigger pulse generator means further includes a counter having output means coupled to said modulator and a third bistable means coupled to said counter, said third bistable means responsive to said reference pulses for enabling said counter and responsive to said trigger pulses for disabling said counter.

12. The apparatus according to claim 11 wherein said trigger pulse generator means further comprises means coupled to said counter for establishing a count representative of said preselected time delay.