Inverter apparatus

• US 4,517,636 A
• Filed: 07/08/1983
• Issued: 05/14/1985
• Est. Priority Date: 07/09/1982
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Nakajima, Kihei, Kurosawa, Ryoichi, Uchino, Hiroshi
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/512,004
• Time in Patent Office: 676 Days
• Field of Search: 363/27, 363/79, 363/96, 363/135, 363/136, 363/137, 363/138, 318/803, 318/807, 318/811
• US Class Current: 363/138
• CPC Class Codes: H02M 7/5155 wherein each commutation element has its own extinguishing means
• CPC Class Codes: H02M 7/525 with automatic control of output waveform or frequency H02M7/517 - H02M7/523 take precedence

Abstract

An inverter apparatus includes a plurality of gate-turn-off thyristors being provided at each end of thyristor-branches, and bias sources or capacitors connected in parallel with the gate-turn-off thyristors for applying reverse voltage to the thyristor-branches when the gate-turn-off thyristor is turned off.

Claims

1. A D.C. to A.C. inverter apparatus responsive to a D.C. power source comprising:

an inverter including thyristor-branches, said inverter being connected across the DC power source;

a plurality of gate-turn-off thyristors respectively interposed between the DC power source and each of the thyristor-branches;

a load connected to the output terminals of said inverter;

gate control means for applying gate turn-off signals to said gate-turn-off thyristors;

means for detecting current through the output terminals of said inverter and applying control signals to said gate control means when the detected current is a predetermined value; and

means for biasing a reverse voltage to the thyristor-branches when said gate-turn-off thyristor is turned off.

2. The inverter apparatus according to claim 1, wherein said biasing means includes a plurality of capacitors, each of said capacitors being respectively connected in parallel with one of said plurality of gate-turn-off thyristors.

3. The inverter apparatus according to claim 1, wherein said biasing means includes a plurality of DC bias sources, each being respectively connected across one of said plurality of said gate-turn-off thyristors.