Fault scoring and selection circuit and method for redundant system

• US 4,517,639 A
• Filed: 05/13/1982
• Issued: 05/14/1985
• Est. Priority Date: 05/13/1982
• Status: Expired due to Fees

• Current Assignee: The Boenig Company
• Original Assignee: The Boeing Co.
• Inventors: Ferrell, Philip J., McFarland, Melvin D., Stern, Alan D.
• Primary Examiner(s): Ruggiero, Joseph F.
• Application Number:
  US06/377,854
• Time in Patent Office: 1,097 Days
• Field of Search: 364/184-187, 364/131-134, 371/8, 371/9, 371/36, 371/16, 371/68, 244/194, 244/195
• US Class Current: 700/81
• CPC Class Codes: G06F 11/1658 Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
• CPC Class Codes: G06F 11/1675 Temporal synchronisation or re-synchronisation of redundant processing components
• CPC Class Codes: G06F 11/181 Eliminating the failing redundant component
• CPC Class Codes: G06F 11/187 Voting techniques

Abstract

In a triplex redundant digital control system, one of three computer units is selected for controlling a digital flight control system by using fault scoring and selection logic circuitry that responds to discrete signals produced by the computer units that represent both self-test and cross-test information on the health of the three available units. The self-test and cross-test discrete information signals are received and processed by the selection logic circuit in accordance with a fault-scoring scheme in which the self-test scores are accorded different and, in particular, greater weight than the cross-test scores and a computer unit exhibiting the lowest combined self- and cross-test fault score is selected as the computer in control. The circuitry also includes memory devices for storing the fault scores associated with previous fault conditions so that a previously unfailed computer unit is selected over a previously failed but currently healthy computer. The memory devices are cleared whenever all three computer modules have scored a fault condition of equal weight such that transient failures do not cause permanent disablement of a computer unit, rather the temporarily faulty unit is allowed to recover and to be brought back on line if needed. To minimize switching, the selection logic causes a new selection only if a computer unit with a lower fault score is available. For simplicity and reliability, the fault scoring and selection logic functions of the circuitry are performed by read-only memories (ROMs) and the memory function is implemented by resettable latches.

Claims

1. A fault scoring and selection circuit for selectively enabling at least one of a plurality of redundant control units to govern the operation of controlled equipment in which the redundant control units are each of the type having both self-testing and cross-testing capabilities respectively producing self-test and cross-test fault signals, said circuit comprising:

fault-scoring logic circuit means including means for receiving self-test and cross-test fault signals from each of said control units, and means assigning predetermined scoring weights, certain of which are different, to said self-test fault signals and cross-test fault signals, and means for combining these weighted fault signals to produce combined fault score signals representing the health of each of said control units; and

selection logic circuit means for receiving said fault score signals, and for converting said fault score signals into a selection output signal that selects at least one of said control units having the lowest available fault score as determined by said fault score signals.

2. The fault scoring and selection circuit of claim 1 wherein said self-test fault signals are each a discrete signal indicating that the corresponding control unit has either failed or not failed its self-test;

and wherein said cross-test fault signals are each discrete signals representing either a failed or nonfailed condition of one of the control units as cross-tested by another of said control units; and

said fault-scoring logic circuit means including means for receiving said self-test and cross-test fault signals in discrete form.

3. The fault scoring and selection circuit of claim 1 wherein said selection logic circuit means comprises means for producing said selection output signal so that said selection output signal selects one of said control units from among those having the lowest available fault score.

4. The fault scoring and selection circuit of claim 1 wherein said means assigning predetermined scoring weights comprises means for assigning a different scoring weight to said self-test fault signals than the scoring weight assigned to said cross-test fault signals.

5. The fault scoring and selection circuit of claim 4 wherein said means assigning said predetermined scoring weights comprises means for assigning a greater scoring weight to each of said self-test fault signals than the predetermined scoring weight assigned to each of said cross-test fault signals.

6. The fault scoring and selection circuit of claim 5 wherein said means assigning predetermined scoring weights comprises means for assigning a scoring weight to each of said self-test fault signals that is twice the predetermined scoring weight assigned to each of said cross-test fault signals such that a subject control unit that has two cross-test faults signalled against it by other control units will have the equivalent of a score resulting from the subject control unit having a failed self-test.

7. The fault scoring and selection circuit of claim 1 in which said fault-scoring logic circuit comprises memory means for storing the state of said fault score signals for each of said control units, said selection logic circuit means being coupled to said memory means for receiving said stored fault score signals so that said selection output signal is produced by said selection logic circuit means in response to previous and present fault scores.

8. The fault scoring and selection circuit of claim 7 wherein said memory means comprises a first memory circuit for storing the state of said fault score signals for each of said control units that results from a single cross-test fault signal, and a second memory circuit for storing the states of said fault score signals for each of said control units that result from a combination of said self-test fault signal or two or more cross-test fault signals being produced against each of said control units.

9. The fault scoring and selection circuit of claim 7 further comprising reset means responsive to said selection logic circuit means and said memory means for resetting said memory means, said reset means being activated in response to a combination of stored fault score signals corresponding to all of said control units having an equal fault score history.

10. The fault scoring and selection circuit of claim 8 further comprising first reset means associated with said first member circuit and second reset means associated with said second memory circuit, said first and second reset means being responsive to said selection logic circuit means and said first and second memory circuits, respectively, such that said first reset means resets said first memory circuit in response to a combination of stored fault score signals corresponding to all of said control units having a single cross-test fault scored against them, and so that said second reset means resets said second memory circuit in response to a combination of stored fault score signals corresponding to all of said control units having a fault score corresponding to a failed self-test or a combination of two cross-test faults.

11. The fault scoring and selection circuit of claim 1 wherein said means assigning predetermined scoring weights to said self-test fault signals and said cross-test fault signals of said fault-scoring logic circuit means comprises means for assigning a single fault scoring weight to each of said cross-test fault signals and a double-fault scoring weight to each of said self-test fault signals, and said means for combining these weighted fault signals comprises means for producing a single fault-scoring signal for each subject control unit in response to one cross-test fault signal indicating a failed condition produced by any of the other control units against the subject control unit, and for producing a double fault-scoring signal for each subject control unit in response to either a failed self-test fault signal from the subject control unit, or two or more cross-test fault signals received from the other control units indicating a failed condition of the subject control unit.

12. The fault scoring and selection circuit of claim 1, in said fault-scoring logic means, said means for combining comprises means for disregarding cross-test fault signals produced by control units that have themselves produced a failed self-test fault signal.

13. The fault scoring and selection circuit of claim 1 wherein said selection logic circuit means comprises means for comparing said fault score signals and when two or more control units share the lowest available fault score, then causing one of these indicated control units to be selected according to predetermined, arbitrary selection rules to ensure that a positive selection of at least one unit is made.

14. The fault scoring and selection circuit of claim 1 wherein said selection logic circuit means comprises means for maintaining the state of said selection output signal unless said fault score signals indicate that a control unit having a lower fault score is available, whereby unnecessary selection switching between control units is avoided.

15. The fault scoring and selection circuit of claim 1 wherein said fault-scoring logic circuit means includes means for producing a multibit binary scoring signal represented by the bits S1, S2, S3, D1, D2 and D3 that is derived from the following set of Boolean relationships:

S1=(2, 2·

2,

     1)+(3, 3·

3,

     1)

S2=(1, 1·

1,

     2)+(3, 3·

3,

     2)

S3=(1, 1·

1,

     3)+(2, 2·

2,

     3)

D1=(1,

     1)+(2, 2·

2, 1·

3, 3·

3,

     1)

D2=(2,

     2)+(1, 1·

1, 2·

3, 3·

3,

     2)

D3=(3,

     3)+(1, 1·

1, 3·

2, 2·

2,

     3)

wherein S1, S2 and S3 are single-fault scores against first, second and third control units, respectively;

D1, D2 and D3 are double-fault scores against said first, second and third control units, respectively; and

the notation set i,j where i=1, 2 or 3 and j=1, 2 or 3, correspond to fault signal identifiers in which 1, 1 is the self-test of the first control unit;

1, 2 is the cross-test by the first control unit against the second control unit;

1, 3 is the cross-test by the first control unit against the third control unit;

2, 1 is the cross-test by the second control unit against the first unit;

2, 2 is the self-test of the second unit;

2, 3 is the cross-test by control unit 2 against unit 3;

3, 1 is the cross-test by control unit 3 against unit 1;

3, 2 is the cross-test by the third control unit against the second unit; and

3, 3 is the self-test against the third control unit and wherein these fault sets, and in which the set i,j equals a binary one when the test signal indicates a failure and equals a binary zero when the test indicates a nonfailed condition.

16. The fault scoring and selection circuit of claim 15 wherein said fault-scoring logic circuit means comprises a first memory means for storing the state of single-fault score signals for each of said control units and a second memory circuit means for storing the state of double-fault score signals for each of said control units, said selection logic circuit means being coupled to said memory means for receiving said stored fault score signals so that said selection output signal is produced by said selection logic circuit means in response to previous (stored) and present fault scores;

and further comprising first and second memory reset means, said first memory reset means resetting said first memory circuit means in response to a combination of stored fault score signals corresponding to all of said control units having a single-fault score (51=1, 52=1 and 53=1), and said second reset means for resetting said second memory circuit memory means in response to a combination of stored fault score signals corresponding to all of said control units having a double-fault score (D1=1, D2=1 and D3=1); and

wherein said single-fault binary bit conditions S1, S2 and S3 are produced in accordance with the following Boolean relationships;

S1=(2, 2·

2,

     1)+(3, 3·

3,

     1)+(S1'"'"'·

RS)

S2=(1, 1·

1,

     2)+(3, 3·

3,

     2)+(S2'"'"'·

RS)

S3=(1, 1·

1,

     3)+(2, 2·

2,

     3)+(S3'"'"'·

RS)

wherein the term S1'"'"' represents a previous (stored) single-fault score for the first control unit, S2'"'"' represents a previous (stored) single-fault score for the second control unit, and S3'"'"' represents a previous (stored) single-fault score for the third control unit, and the term RS represents the nonresetting of said first memory circuit means by said first reset circuit; and

wherein the double-fault scoring bits D1, D2 and D3 are derived from the following Boolean relationships;

D1=(1,

     1)+(2, 2·

2, 1·

3, 3·

3,

     1)+(D1'"'"'·

RD)

D2=(2,

     2)+(1, 1·

1, 2·

3, 3·

3,

     2)+(D2'"'"'·

RD)

D3=(3,

     3)+(1, 1·

1, 3·

2, 2·

2,

     3)+(D3'"'"'·

RD)

wherein the term D1'"'"' represents a previous (stored) double-fault bit state for the first control unit, D2'"'"' represents a previous (stored) double-fault bit state for the second control unit and D3'"'"' represents a previous (stored) double-fault state for the third control unit, and RD represents the nonresetting of said second memory circuit means by said second reset circuit.

17. The fault scoring and selection circuit of claim 16 wherein said selection logic circuit means includes means responsive to said multibit scoring word of S1, S2, S3, D1, D2 and D3 to produce a two-bit binary selection signal that selects one of said plurality of control units.

18. The fault scoring and selection circuit of claim 1 wherein said fault-scoring logic circuit means comprises a read-only memory (ROM) programmed to produce said combined fault score signals in response to said self-test and cross-test fault signals.

19. The fault scoring and selection circuit of claim 1 wherein said selection logic circuit means comprises a read-only memory (ROM) that is programmed to receive said fault score signals and to convert said fault score signals into said selection output signal.

20. The fault scoring and selection circuit of claim 19 wherein said fault scoring logic circit means comprises resettable latches coupled to said read-only memory for storing the state of said fault score signals for each of said control units, and further comprises reset circuit means for resetting said latches in response to a predetermined combination of stored fault score signals.

21. A redundant computer control system for reliable operation of computer-controlled equipment comprising in combination:

a plurality of redundant computer units, each of said computer units including means for producing a self-test fault signal in discrete format indicating either a faulty or nonfaulty self-test state, and means for producing a plurality of cross-test fault signals in discrete format, one such cross-test fault signal being produced for each other of said plurality of computer units and indicating that such other control unit has either a faulty or nonfaulty state;

fault scoring and selection circuitry for selectively enabling at least one of said plurality of computer units to control the equipment, said fault scoring and selection circuitry comprising;

fault-scoring logic circuit means including means for receiving said self-test and cross-test fault signals and means for assigning predetermined scoring weights, certain of which are different, to said self-test fault signals and to said cross-test fault signals, and means for combining these weighted fault signals to produce combined fault score signals representing the health of each of said computer units; and

selection logic circuit means for receiving said fault score signals, and for converting said fault score signals into a selection output signal that selects at least one of said computer units that has the lowest available fault score as determined by said fault score signals.

22. A method of selecting at least one of a plurality of redundant control units to govern the opeation of controlled equipment by automatic fault scoring and selection logic, in which each of the plurality of redundant interlinked control units is of the type capable of producing both a self-test discrete signal representing a failed or nonfailed self-test and cross-test discrete signals corresponding to failed or nonfailed conditions of the other control units, comprising the combination of steps of:

receiving and scoring the self-test and cross-test discrete signals from said control units by assigning predetermined scoring weights, certain of which are different, to said self-test fault signals and to said cross-test fault signals, and combining these weighted fault signals to produce combined fault score signals representing the health of each of said control units; and

selecting at least one control unit by comparing said combined fault score signals in accordance with predetermined selection logic, and responsively producing a selection output signal that selects at least one of said control units having the lowest available fault score as determined by said fault score signals.

23. The method of claim 22 wherein said step of assigning said predetermined scoring weights comprises the substeps of assigning a different and greater scoring weight to said self-test fault signals than the predetermined scoring weight assigned to said cross-test fault signals.

24. The method of claim 22 further comprising the step of storing in memory, the fault score signals produced by the step of receiving and scoring said self-test and cross-test signals, and wherein the step of selecting comprises the substeps of producing said selection output signal in response to the stored fault score signals so that said selection output signal is responsive to both previous and present fault scores.

25. The method of claim 24 wherein said step of storing the fault score signals in memory comprises the addition step of resetting said memory in response to a combination of stored fault score signals corresponding to all of said computer units having a like fault score history.