Double polysilicon process for fabricating CMOS integrated circuits

• US 4,517,731 A
• Filed: 09/29/1983
• Issued: 05/21/1985
• Est. Priority Date: 09/29/1983
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: Fairchild Camera and Instrument Corporation (ON Semiconductor Corporation)
• Inventors: Khan, Mahboob, Trieu, Tom
• Primary Examiner(s): NOT, DEFINED
• Assistant Examiner(s): Auyang, Hunter L.
• Application Number:
  US06/537,188
• Time in Patent Office: 600 Days
• Field of Search: 29/571, 29/577 C, 29/578, 148/1.5, 357/23 CS, 357/44, 357/59
• US Class Current: 438/210
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A process is disclosed for fabricating complementary n and p channel insulated gate field effect transistors. The process uses two layers of polycrystalline silicon 32 and 44 to provide electrical interconnections, and allows the formation of microcapacitors between the two layers of polycrystalline silicon. In addition silicon dioxide and silicon nitride, and two layers of photoresist, are used as masks against heavy boron implantations. The reliability of ohmic connections between aluminum 50 and contact regions in the substrate is enhanced by providing additional dopant to the contact regions. In this way, the junction depth is increased and electrical defects caused by metal spiking are minimized.

Claims

1. In a process for fabricating complementary field effect transistors (FET) wherein a first FET is formed in a well of first conductivity type in a semiconductor substrate of opposite conductivity type, a method for enhancing the field threshold of the first FET comprising:

forming a first layer of insulating material over the well;

forming a second layer of insulating material over a selected portion of the first layer, the selected portion being disposed over the well, but spaced apart from opposing sides of the well;

forming masking material over all of the second layer, and all of the first layer except an intervening region of the first layer between the selected portion and the opposing sides of the well; and

introducing first conductivity type impurity into the intervening region.

2. A method as in claim 1 wherein the first layer comprises silicon dioxide.

3. A method as in claim 2 wherein the second layer comprises silicon nitride.

4. A method as in claim 3 wherein the masking material comprises photoresist.

5. A method as in claim 1 wherein the first conductivity type is p conductivity type.

6. A method as in claim 1 followed by the steps of:

forming field oxide regions adjacent the p-type region and the portion of the substrate within which the n-channel transistor will be formed; and

non-selectively introducing p-type dopant into the p-type region and the substrate.

7. In a process for fabricating complementary n-channel and p-channel insulated gate field effect transistors wherein said n-channel transistor is formed in a region of p-type conductivity within a substrate of n-type semiconductor material and said p-channel transistor is formed within the n-type substrate, a method for forming self-aligned n-channel field regions to independently enhance the field threshold of said n-channel transistor, comprising:

a. forming a layer of silicon oxide over the substrate;

b. forming a region of silicon nitride on the oxide layer such that portions of the oxide layer adjacent the nitride region and overlying the p-type region remain exposed;

c. forming a region of first photoresist overlying the nitride region;

d. forming a layer of second photoresist over said structure formed according to steps (a) through (c) above and patterning the second photoresist layer to expose the first photoresist region and the portions of the oxide layer adjacent the nitride region and overlying the p-type region; and

e. introducing p-type impurity into the p-well beneath the portions of the oxide layer.

8. A method as in claim 7 including the subsequent additional steps of fabricating capacitors comprising:

a. forming regions of first conductive polycrystalline silicon over the complementary transistors;

b. forming a layer of insulating material of desired thickness over the first polycrystalline silicon; and

c. forming regions of second conductive polycrystalline silicon over the layer of insulating material and over the underlying regions of first polycrystalline silicon wherever capacitors are desired.

9. A method for fabricating complementary n-channel and p-channel insulated gate field effect transistors, comprising:

a. forming a p-type well in a substrate of n-type silicon which p-well is contiguous with a major surface of the substrate;

b. forming a layer of silicon oxide over the major surface;

c. forming a first region of silicon nitride on the oxide overlying the p-well such that portion of the oxide adjacent the first nitride region and overlying p-well remain exposed and a second region of silicon nitride on the oxide overlying a second portion of the substrate;

d. forming first and second regions of first masking material over the first and second regions of nitride, respectively;

e. forming a layer of second masking material over the first and second regions of first masking material and the oxide and defining the second masking material layer to re-expose portions of the oxide adjacent the first nitride region and overlying the p-well;

f. introducing p-type impurity into the p-well through the exposed oxide;

g. removing the first and second masking material and non-selectively introducing n-type impurity into the substrate;

h. forming field oxide regions adjacent the p-well and the second portion of the substrate to electrically isolate the p-well and the second portion of the substrate;

i. non-selectively introducing p-type impurity into the p-well and the second portion of the substrate;

j. forming first, second and third regions of conductive first polycrystalline silicon on the oxide overlying the p-well, on the oxide overlying the second portion of the substrate, and on selected of the field oxide regions, respectively;

k. utilizing silicon nitride as a mask, selectively introducing n-type impurities into the p-well to form source and drain regions of the n-channel transistor;

l. selectively introducing p-type impurity into the second substrate portion to form source and drain regions of the p-channel transistor;

m. forming regions of second polycrystalline silicon in contact with selected of the first polysilicon regions and n-type regions of such substrate;

n. forming regions of metal in contact with selected second polycrystalline silicon regions, first polycrystalline silicon regions, and different n-type and p-type regions of said substrate.

10. A method for fabricating a complementary insulated gate field effect transistor structure wherein n-channel and p-channel transistors are formed within the same semiconductor substrate, comprising:

a. forming an initial layer of silicon oxide on a major surface of a substrate of n-type silicon;

b. removing a portion of the initial silicon oxide layer to define a first preselected portion of the surface;

c. introducing p-type impurity into the first preselected surface portion to form a lightly-doped p-well region in the substrate, the p-well region being contiguous with the major surface of the substrate;

d. removing the remaining initial silicon oxide layer and forming a first thin oxide layer on the surface;

e. forming a first region of silicon nitride on the first thin oxide layer over a portion of the p-well region and a second region of silicon nitride on the first thin oxide layer over a second preselected portion of the surface;

f. forming a first photoresist layer over the wafer and patterning the first photoresist layer to form photoresist regions over the first and the second silicon nitride regions;

g. forming a second layer of photoresist over the wafer and patterning and etching the wafer to expose first and second portions of the thin oxide layer overlying the p-well region which first and second portions are adjacent the first silicon nitride region and the overlying first photoresist region;

h. implanting p-type impurities into the substrate beneath the first and second portions of the thin oxide layer;

i. removing remaining portions of the first and second photoresist layers;

j. implanting n-type impurities into the surface except beneath the first and second silicon nitride regions;

k. removing the first and second nitride regions and the thin oxide layer;

l. forming field oxide regions and adjacent the first and second preselected surface regions to selectively isolate the portions;

m. forming gate oxides over the first and second preselected surface regions;

n. forming a third layer of photoresist over the wafer and patterning the etching the third photoresist layer to expose the gate oxide overlying selected areas of the first surface regions;

o. implanting n-type impurity into the selected areas of first surface regions;

p. forming a first layer of p-type polysilicon over the wafer and patterning and etching the first polysilicon layer to form a first region of first polysilicon overlying the first preselected surface region, a second region of first polysilicon overlying the second preselected surface region, and third regions of first polysilicon overlying selected of the field oxide regions;

q. implanting n-type impurity into the p-well region adjacent the first region of first polysilicon to form n-type source and drain regions for the n-channel transistor;

r. implanting p-type impurity into the second preselected surface portion adjacent the second region of first polysilicon to form p-type source and drain regions for the p-channel transistor;

s. forming a first polyoxide layer over the first, second and third regions of first polysilicon and patterning the oxide to form contact holes to selected first polysilicon regions and selected n-type source and drain regions;

t. forming a second layer of polysilicon on the wafer to make contact with the selected of the first polysilicon regions and the selected n-type source and drain regions;

u. forming a second polyoxide layer over the second layer of polysilicon and patterning the second polysilicon and polyoxide layer;

v. forming a layer of phosphosilicate glass over the second polyoxide layer and patterning and etching the glass layer to form contact holes to selected second polysilicon regions, different first polysilicon regions, different n-type regions and the p-type regions;

w. forming metal contacts to said selected second polysilicon layer, different first polysilicon layer, different n-type regions, and the p-type regions, and

x. forming a protective layer over the wafer.