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Double polysilicon process for fabricating CMOS integrated circuits

  • US 4,517,731 A
  • Filed: 09/29/1983
  • Issued: 05/21/1985
  • Est. Priority Date: 09/29/1983
  • Status: Expired due to Term
First Claim
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1. In a process for fabricating complementary field effect transistors (FET) wherein a first FET is formed in a well of first conductivity type in a semiconductor substrate of opposite conductivity type, a method for enhancing the field threshold of the first FET comprising:

  • forming a first layer of insulating material over the well;

    forming a second layer of insulating material over a selected portion of the first layer, the selected portion being disposed over the well, but spaced apart from opposing sides of the well;

    forming masking material over all of the second layer, and all of the first layer except an intervening region of the first layer between the selected portion and the opposing sides of the well; and

    introducing first conductivity type impurity into the intervening region.

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