Apparatus for storing and processing analogue signals to be displayed as an oscilloscopic image and oscilloscope comprising such apparatus

• US 4,518,991 A
• Filed: 09/22/1982
• Issued: 05/21/1985
• Est. Priority Date: 09/28/1981
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Dureux, Pierre J. C.
• Primary Examiner(s): Martin, John C.
• Assistant Examiner(s): Coles, Edward L.
• Application Number:
  US06/421,609
• Time in Patent Office: 972 Days
• Field of Search: 358/244, 358/244.1, 358/93, 358/222, 358/160, 358/166, 358/167, 358/139, 358/107, 358/168, 358/169, 358/174, 350/20
• US Class Current: 348/61
• CPC Class Codes: G01R 13/32 Circuits for displaying non-recurrent functions such as transients; Circuits for triggering; Circuits for synchronisation; Circuits for time-base expansion

Abstract

An apparatus for the storage and processing of analog signals which are stored temporarily in an analog memory, formed by the target of a camera, is provided with the analog signals being converted into video frequency signals by means of a video scanning system of the camera. The signals are subsequently processed by a processing circuit comprising digitizing, storage and restitution circuits, a monitor forming the actual display means for the oscilloscopic image, a sequencer control circuit which carries out the principal synchronization and control functions, and an operator control panel.

Claims

1. An apparatus for storing and processing arbitrary analog signals comprising

a camera having a target providing images for a temporary analog memory, said camera including a video scanning system for scanning said temporary analog memory, and a video preamplifier for converting electrical signals of said images into video frequency signals;

and

a processing circuit receiving signals from said video preamplifier for processing said video frequency signals, said processing circuit including

(a) a detection circuit for detecting an average black level value corresponding to used parts of said temporary analog memory, said detection circuit receiving output signals from said video preamplifier, and said detector circuit generating a reference threshold value by adding a constant voltage to said detected average black level value;

(b) an analog comparator circuit for receiving said output signals of said video preamplifier on a first input and for receiving said reference threshold value on a second input, said comparator circuit for providing a logic "1" signal only when said output values exceed said reference threshold value,

(c) a signal regenerator circuit receiving a signal from said analog comparator circuit for reconstructing missing parts of maximum instantaneous write signals, said missing parts having a duration shorter than a predetermined value, said signal regenerator circuit providing a binary signal representing said missing parts;

(d) a conversion circuit for converting said binary signal into a pulse train of the same duration as said missing parts, said duration being equal to at least a few pulse periods of said pulse train for restoring said missing parts, said conversion circuit providing an output signal;

(e) a change detector circuit for detecting positions of rising and falling edges of said output signal of said conversion circuit, said change detector circuit supplying pulse signals indicating beginnings and ends of said missing parts;

(f) a digital memory circuit for storing positions of said beginnings and ends of said missing parts, said memory circuit being loaded by an input buffer register having quantized values being defined by a digitization counter, said values indicating positions of said pulse signals providing beginnings and ends of said missing parts;

(g) a circuit for restitution of positions of instants characteristic of a beginning or an end of a missing part, said restitution circuit receiving values read into said digital memory circuit by an output buffer register circuit;

(h) a circuit for reconstructing said missing parts between positions of said beginnings and ends of said missing parts;

(i) a television monitor means for forming display of said images, said monitor means enabling display of contents of said digital memory circuit permanently, said contents being information corresponding to write signals in said temporary analog memory;

(j) a sequence control circuit providing a synchronous supply of clock signals for scanning said temporary analog memory and clock signals for converting said binary signal of said signal regenerator, said sequence control circuit controlling clock signals for said digital memory circuit, and said sequence control circuit providing an entire operator write circuit communication; and

(k) an accessible control panel.

2. An oscilloscope comprising an apparatus according to claim 1.

3. An apparatus according to claim 1, further comprising a first auxiliary circuit being an acquisition-quality detection circuit, wherein said first auxiliary circuit includes a circuit for determining a quality factor having a value related to the time that said video frequency signal has an amplitude exceeding said reference threshold value, said quality factor being stored in said digital memory circuit at the same time as associated principal data corresponding to a write signal in said temporary analog memory, and a comparator circuit for comparing quality factors of a line just stored and of said same line stored in said digital memory circuit during an arbitrary previous time, said associated principal data being data to which the highest quality factor is attributed after the comparison by said comparator circuit.

4. An apparatus according to claim 1 or claim 3, wherein a computer is arranged in parallel with said digital memory circuit for carrying out additional processing.

5. An apparatus according to claim 1 or claim 3, further comprising a second auxiliary circuit being a rate-of-visibility detection circuit, wherein said second auxiliary circuit includes a digital circuit for determining cumulative lengths of segments for a given television line effected by said camera from each contents consecutively read from said digital memory circuit, a digital-to-analog converter, a circuit for adapting a brightness modulation profile, and a modulation circuit for carrying out analog multiplication of respective output signals of said reconstructing circuit and of said brightness modulation profile circuit, said modulation circuit supplying signals to said television monitor means.

6. An apparatus according to claim 5, further comprising a third auxiliary circuit being switchable, wherein said third auxiliary circuit provides direct transfer of output signals of said video preamplifier to said television monitor means, and wherein said third auxiliary circuit operates only when said reference threshold value is not reached for a sufficiently long time and when storage by said digital memory circuit is no longer possible even though said output signals of said video preamplifiers permit a visible image to be obtained.

7. An apparatus according to claim 6, wherein a computer is arranged in parallel with said digital memory circuit for carrying out additional processing.

8. An apparatus according to claim 5, wherein a computer is arranged in parallel with said digital memory circuit for carrying out additional processing.

9. An apparatus according to claim 1 or claim 3, further comprising a third auxiliary circuit being switchable, wherein said third auxiliary circuit provides direct transfer of output signals of said video preamplifier to said television monitor means, and wherein said third auxiliary circuit operates only when said reference threshold value is not reached for a sufficiently long time and when storage by said digital memory circuit is no longer possible even though said output signals of said video preamplifiers permit a visible image to be obtained.

10. An apparatus according to claim 9, wherein a computer is arranged in parallel with said digital memory circuit for carrying out additional processing.