Phase-locked loop and clock circuit for a line switch

• US 4,519,071 A
• Filed: 04/22/1982
• Issued: 05/21/1985
• Est. Priority Date: 04/22/1982
• Status: Expired due to Term

• Current Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Original Assignee: International Telephone and Telegraph Corporation
• Inventors: Miller, Robert L.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US06/370,602
• Time in Patent Office: 1,125 Days
• Field of Search: 370/100, 375/120
• US Class Current: 370/503
• CPC Class Codes: H04J 3/0685 Clock or time synchronisation in a node; Intranode synchronisation
• CPC Class Codes: H04J 3/0688 Change of the master or reference, e.g. take-over or failure of the master
• CPC Class Codes: H04Q 11/0407 using a stored programme control

Abstract

A line switch for a digital telephone switching system utilizes distributed processing. The line switch comprises one or more switch modules. Each switch module is coupled to a central office switching system via one or more PCM lines which utilize common channel signaling. Each switch module comprises groups of line circuits, each line circuit being coupled to a subscriber line. Three separate distributed processor functions are provided in each line switch module. First one processor is utilized to communicate with the central office switching system and to coordinate the operations within the line switch module. A second processor is provided to control clock generation and rate conversion circuits. Each group of line circuits includes a third processor to control the operations of the line circuits and to gather information from the line circuit.

The second processor is used to select which of a plurality of sources may be used to provide clock signals within the line switch module.

A phase-locked loop permits clock signals which are generated in a line switch module to be in phase synchronism with any one of the PCM lines. When two or more lines switch modules are connected together to form a line switch, the phase-locked loop circuits of each module will utilize the same PCM line for phase-locking.

Claims

1. A circuit arrangement responsive to an input signal of a first frequency at a first terminal for generating output signals of a second frequency and having a predetermined phase relationship to said input signals at a second terminal, said circuit arrangement comprising:

a voltage controlled oscillator having an output coupled to said second terminal and having a control input, said voltage controlled oscillator generating a signal having a frequency dependent on the voltage level at said control input;

means coupled to said voltage controlled oscillator output for supplying feedback signals; and

first means responsive to said input signals and said feedback signals for supplying said voltage level, said first means comprising;

a controlled voltage source for generating said voltage level in response to first and second control signals, said controlled voltage source being responsive to said first control signal to change said voltage level in a first direction and being responsive to said second control signal to change said voltage level in a second direction opposite said first direction; and

detection means for generating said first and second control signals in response to said input signals and said feedback signals, said detection means having a first stable state whereby neither said first nor said second control signals are generated, a second stable state whereby only said first control signal is generated, and a third stable state whereby said second control signal is generated, said detection means normally being in said first stable state, said detection means assuming said second stable state each time said input signal occurs prior to said feedback signal and remaining in said second stable state for substantially the time difference between the occurrences of said input signal and said feedback signal, said detection means returning to said first stable state from said second stable state after the occurrence of said feedback signal, said detection means assuming said third stable state each time said feedback signal occurs prior to said input signal and remaining in said third stable state for substantially the time difference between the occurrence of said feedback signal and said input signal, said detector means returning to said first stable state from said second stable state after the occurrence of said input signal.

2. A circuit arrangement in accordance with claim 1, wherein said detection means comprises:

first bistable means having first and second conductive states and being responsive to the occurrence of said input signal for switching from said first conductive state to said second conductive state, said first bistable means having an output for providing said first control signal when in said second conductive state;

second bistable means having first and second conductive states and being responsive to the occurrence of said feedback signal for switching from said first conductive state to said second conductive state, said second bistable means having an output for providing said second control signal when in said second conductive state; and

means responsive to said first and second bistable means concurrently having said second conductive state for resetting each of said first and second bistable means to said first conductive state.

3. A circuit arrangement in accordance with claim 1 or 2, wherein said voltage controlled source comprises:

a voltage integrator having an output coupled to said control input, a first input for receiving said first control signal and a second input for receiving said second control signal.

4. A circuit arrangement in accordance with claim 3, wherein said voltage integrator comprises:

capacitor means;

first switch means responsive to one of said first and second control signals for supplying charging current to said capacitor means; and

second switch means responsive to the other of said first and second control signals for discharging said capacitor means.

5. A circuit arrangement in accordance with claims 1 or 2, wherein said second frequency is higher than said first frequency;

and said feedback means comprises frequency dividing means for frequency dividing said output signals by a predetermined factor to generate said feedback signals.

6. A circuit arrangement in accordance with claim 3, wherein said second frequency is higher than said first frequency;

and said feedback means comprises frequency dividing means for frequency dividing said output signals by a predetermined factor to generate said feedback signals.

7. A circuit arrangement in accordance with claim 4, wherein said second frequency is higher than said first frequency;

and said feedback means comprises frequency dividing means for frequency dividing said output signals by a predetermined factor to generate said feedback signals.

8. A circuit arrangement in accordance with claim 2, wherein said first and second bistable means each comprises an edge-triggered flip-flop.

9. A circuit arrangement responsive to input signals of a first frequency for generating at an output terminal output signals of a second frequency having a predetermined phase relationship to said input signals, said circuit arrangement comprising:

a voltage controlled oscillator having a voltage control input and an output coupled to said output terminal;

means coupled to said voltage controlled oscillator output for providing a feedback signal;

a detection circuit comprising first bistable means having first and second conductive states and being responsive to the occurrence of said input signal for switching from said first conductive state to said second conductive state, and second bistable means having first and second conductive states and being responsive to the occurrence of said feedback signals for switching from said first conductive state to said second conductive state, and reset means for resetting said first and second bistable means to said first conductive state after said first and second bistable means are both switched to said second state; and

voltage control means for generating a control voltage at said voltage control input, said voltage control means comprising first means for increasing the voltage level of said control voltage in response to one of said first and second bistable means having said second conductive state and for decreasing the voltage level of said control voltage in response to the other one of said first and second bistable means having said second conductive state.

10. A circuit arrangement in accordance with claim 9, wherein said voltage control means comprises capacitor means;

first electronic switch means; and

second electronic switch means, said first electronic switch means being responsive to said one of said first and second bistable means having said second conductive state for supplying a charging current to said capacitor means, said second electronic switch means being responsive to said other one of said first and second bistable means having said second conductive state for discharging current from said capacitor means.

11. A circuit arrangement in accordance with claim 9 or 10, wherein said first and second bistable means each comprises an edge-triggered flip-flop.

12. A circuit arrangement in accordance with claim 10, wherein said capacitor means comprises a low-pass filter.

13. A circuit arrangement in accordance with claim 10, wherein said first electronic switch comprises a transistor having a control terminal coupled to said one of said first and second bistable means, a second terminal coupled to a first polarity voltage, and a third terminal coupled to said capacitor means;

and

said second electronic switch comprises a transister having a control terminal coupled to said other one of said first and second bistable means, a first terminal coupled to a second polarity voltage, and a third terminal coupled to said capacitor means.

14. A circuit for receiving at an input terminal PCM framing clock pulses at one frequency and for generating at an output terminal second PCM bit clock pulses at a second frequency, said circuit comprising:

voltage controller oscillator means having an output coupled to said output terminal and a control input, said voltage controlled oscillator means generating said second PCM bit clock pulses at a frequency dependent on the voltage level at said control input;

feedback means coupled to said oscillator means output for dividing the frequency of said second PCM bit clock pulses by a predetermined factor to generate feedback clock pulses;

phase detector means for generating error current when said feedback clock pulses are out of phase with said framing clock pulses;

loop filter means for integrating said error currents to generate said voltage level; and

means for deriving said PCM framing clock pulses from first PCM bit clock pulses.

15. A circuit in accordance with claim 14, wherein said deriving means comprises a dividing circuit for dividing said first PCM bit clock pulse by a first predetermined factor to generate said PCM framing clock pulses.

16. A circuit in accordance with claim 15 wherein said dividing circuit is synchronized by signalling frame identification pulses.

17. A circuit in accordance with claims 14, 15, or 16, wherein said phase detector means has first, second and third stable states, said phase detector assuming said second stable state each time one pulse of said framing clock pulses precedes one corresponding pulse of said feedback clock pulses, said phase detector assumes said third stable state each time said corresponding pulse precedes said one pulse,

said phase detector assumes said first stable state after the occurrence of both said one pulse and said corresponding pulse,

said phase detector means generating a first error current when in said second stable state and generating a second error current when in said third stable state.

18. A circuit in accordance with claim 17, wherein said loop filter means is responsive to said first error current to change said voltage level in a first direction and responsive to said second error current to change said voltage level in a second direction.

19. A circuit in accordance with claim 17, wherein said phase detector comprises a first bistable element having an input adapted to receive said framing clock pulses and a second bistable element having an input adapted to receive said feedback clock pulses, said first bistable element assuming a first stable state when said one pulse precedes said corresponding pulse, said second bistable element assuming a first stable state when said corresponding pulse precedes said one pulse, said first bistable element switching to a second stable state and said second bistable element switching to a second stable state after the occurrence of both said one and said corresponding pulses.

20. A circuit in accordance with claim 19, wherein said first bistable element comprises a first edge-triggered flip-flop and said second bistable element comprises a second edge-triggered flip-flop;

and

said phase detector comprises means for resetting said first and second flip-flops to said respective second stable states after the occurrence of said both said one and said corresponding pulses.

21. A circuit arrangement in accordance with claim 20, wherein said resetting means comprises gating means having a first input coupled to said first flip-flop, a second input coupled to said second flip-flop, and a reset output coupled to said first and second flip-flops.