MOS Phase lock loop synchronization circuit

• US 4,519,086 A
• Filed: 06/16/1982
• Issued: 05/21/1985
• Est. Priority Date: 06/16/1982
• Status: Expired due to Fees

• Current Assignee: Western Digital Corporation
• Original Assignee: Western Digital Corporation
• Inventors: Hull, Richard W., Teslenko, Leonard
• Primary Examiner(s): Safourek, Benedict V.
• Application Number:
  US06/388,899
• Time in Patent Office: 1,070 Days
• Field of Search: 331/57, 331/175, 331/176, 331/108 C, 331/177 R, 331/1 A, 328/61, 328/63, 328/209, 328/133, 328/155, 307/491, 307/494, 307/497, 307/289, 375/120, 375/80, 375/81, 375/82, 375/119, 360/51, 329/104, 329/110, 329/122, 329/124
• US Class Current: 375/376
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: Y10S 331/03 Logic gate active element oscillator

Abstract

A metal oxide semiconductor (MOS) phase lock loop data synchronization circuit, for use in conjuction with an integrated circuit disk controller device, comprising a temperature, process, and voltage compensated MOS voltage controlled oscillator (VCO), a three-bit counter, and a phase detector circuit. The phase detector circuit compares a decoded clock signal output from the VCO with incoming data from a disk device to detect phase differences between the frequency of the VCO and the actual frequency of the incoming data. The phase detector produces voltage signals in response to any such phase differences, which are coupled to the VCO and alter the frequency output of the VCO to match the frequency of the incoming data. The counter provides a system read-clock, which is fully synchronized with the incoming data, to an integrated circuit disk controller device which further processes the data.

Claims

1. An improved phase detector circuit comprising:

(a) a variable voltage controlled oscillator having a variable resistance means for varying the frequency of the oscillator output signal in response to a voltage correction signal;

(b) counter means for receiving the output signal from the oscillator, for generating during each four clock cycles of the oscillator output signal a first phase detection enable signal during every fourth clock cycle, and a second phase detection enable signal during every first and second clock cycles, and further for generating a clock output;

(c) a signal shaping means for receiving a data input signal of approximately the same frequency as the clock output of the counter means and for generating an approximately uniform width data output signal;

(d) a first logical AND gate means for receiving the data output signal and the first phase detection enable signal and generating a first phase difference signal;

(e) a second logical AND gate means for receiving the data output signal and the second phase detection enable signal and generating a second phase difference signal; and

(f) a switchable voltage pulse generator comprising first and second transistor means in series coupled respectively to the output of said first and second logical AND gates, with the junction of the first and second transistors being coupled to the variable resistance means of the oscillator, for generating and transmitting a voltage correction signal to the variable resistance means of the oscillator in response to the presence of the first or second phase difference signals, wherein the voltage correction signal causes the variable resistance means to change the frequency output of the variable voltage controlled oscillator, thereby causing the clock output of the counter means to become synchronized with the frequency of the input data signal.

2. An improved metal oxide semiconductor (MOS) 5-stage voltage controlled ring oscillator, comprising:

(a) A two-part first stage comprising an inverter for receiving a feed-back signal, and a differential voltage comparator means for receiving the feedback signal and a reference voltage signal and adapted to compensate for variations in the threshold voltage of the MOS devices used in the ring oscillator caused by changes in temperature, voltage, or fabrication processing parameters;

(b) a second stage comprising an inverter coupled to the output of the differential voltage comparator of the first stage;

(c) a third stage comprising a cross-coupled latch circuit, coupled to the output of the inverter of the first stage and to the output of the second stage, for preventing loss of oscillation in the ring oscillator;

(d) a fourth stage comprising a logical NOR gate coupled to an output of the third stage and to the output of the second stage;

(e) a fifth stage comprising a logical NOR gate coupled to a second output of the third stage and to the fourth stage; and

(f) a variable resistance means connecting the fifth stage of the ring oscillator to the first stage, for providing the feed-back signal to the first stage and for varying the frequency of the ring oscillator output signal in response to an external voltage signal, wherein the variable resistance means is adapted to compensate for variations in the threshold voltage of the MOS devices used in the ring oscillator and caused by changes in temperature, voltage, or fabrication processing parameters.