Polygraphic encryption-decryption system

• US 4,520,232 A
• Filed: 04/30/1982
• Issued: 05/28/1985
• Est. Priority Date: 04/30/1982
• Status: Expired due to Fees

• Current Assignee: William J. Wilson
• Original Assignee: William J. Wilson
• Inventors: Wilson, William J.
• Primary Examiner(s): Cangialosi, Sal
• Application Number:
  US06/373,341
• Time in Patent Office: 1,124 Days
• Field of Search: 178/22.05, 178/22.09, 178/22.19
• US Class Current: 380/28
• CPC Class Codes: H04L 2209/125 Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
• CPC Class Codes: H04L 9/0618 Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation

Abstract

A system for encoding, or encrypting, digital data wherein an invertible matrix of binary bits provides the encrypting factor or key, this invertible matrix being loaded in a memory. Blocks or sets of binary bits of data, a string of serially appearing binary bits, to be encoded are sequentially loaded into discrete, ordered stages of an input shift register, and the state of each stage is coupled as an enabling signal to sets of gates which read out the binary states of rows of the matrix configured memory. Groups of outputs from gates, conforming to columns of the matrix memory, are fed to an exclusive OR gate for each group. Then, the outputs of the exclusively OR gates for several columns of the matrix are loaded into discrete stages of an output register. The combination of the states of the output register together provide a block or polygraphic encryption, or decryption, of the binary data supplied the input register. The states of the output register are then clocked out in serial form.

Claims

1. A binary encryption/decryption system comprising:

buffer storage means having a selected plurality of ordered binary storage locations, and responsive to a series of binary state input signals, for selectively and temporarily storing, in order of appearance, sets of said series of input signals in correspondingly ordered storage locations;

key storage means comprising;

a plurality of binary signal memory locations, and there being stored therein an invertible binary matrix of ordered rows and columns having a common row and column origin, and

readout means, including a plurality of row oriented sets of electronic gating means, one set for each row of memory locations, each electronic gating means of a set being coupled to a separate memory location of the same row, and being responsive to a selected state of binary signal control input for gating to an output the binary state of the memory location to which the gate is coupled;

coupling means for supplying the signal state of each discretely ordered storage location of said buffer storage means, as a control input, to a row oriented discrete set of electronic gating means for a said row of said matrix, whereby, where said selected signal state is present in one of said ordered storage locations of said buffer storage means, the signal state of a coordinately ordered row of said matrix appears across the outputs of a said set of electronic gating means, and where a non-selected state exists, the gating means of a coordinate set of electronic gating means for a row of said matrix each provides a like state output and do not, together, gate out the signal states of a row of memory locations as outputs;

a set of row oriented exclusively OR logic circuit means, each said logic circuit means being responsive to a column oriented set of outputs of said electronic gating means for providing, in a selected order, an ordered set of modulo 2 character output signals; and

signal means responsive to successively following sets of said ordered output signals for providing said last-named output signals as a series of sets of binary output signals;

whereby sets of said ordered series of binary state input signals are translated, in mass, into encrypted sets of a like ordered series of binary state output signals.

2. A communications system comprising:

first and second communications stations;

communications signal transmission means for the transmission of first signals from said first station to said second station and for transmission of said second signals from said second station to said first station;

said first and second stations each comprising;

buffer storage means having a selected plurality of ordered binary storage locations, and responsive to a series of binary state input signals, including signals derived from said communications signal transmission means, for selectively and temporarily storing, in order of appearance, successive sets of said series of input signals in correspondingly ordered storage locations,

key storage means comprising;

a plurality of binary signal memory locations, and there being stored therein an invertible binary matrix of ordered rows and columns having a common row and column origin, and

readout means including a plurality of row oriented sets of electronic gating means, one set for each row of memory locations, each electronic gating means of a set being coupled to a separate memory location of the same row, and being responsive to a selected state of binary signal control input, for gating to an output the binary state of the memory location to which the gate is coupled,

coupling means for supplying the signal state of each discretely ordered storage location of said buffer storage means, as a control input, to a row oriented discrete set of electronic gating means for a said row of said matrix, whereby, where said selected signal state is present in one of said ordered storage locations of said buffer storage means, the signal states of a coordinately ordered row of said matrix appears across outputs of a said set of electronic gating means, and, where a non-selected state exists, each gating means of a coordinate set of electronic gating means for a row of said matrix provides a like state output, and do not, together, gate out the signal states of a row of memory locations as outputs;

a set of row oriented exclusively OR logic circuit means, each said logic circuit means being responsive to a column oriented set of outputs of said electronic gating means for providing, in a selected order, an ordered set of modulo 2 character output signals, and

signal means responsive to successively following said ordered set of modulo 2 character output signals for providing said last-named output signals as a series of sets of binary output signals to said communication means; and

said invertible matrix of said key storage means of said first station is the inverse of said invertible matrix of said key storage means of said second station.