Secure microprocessor/microcomputer with secured memory

• US 4,521,853 A
• Filed: 06/30/1982
• Issued: 06/04/1985
• Est. Priority Date: 06/30/1982
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Guttag, Karl M.
• Primary Examiner(s): Heckler, Thomas M.
• Assistant Examiner(s): Dorsey, Daniel K.
• Application Number:
  US06/393,956
• Time in Patent Office: 1,070 Days
• Field of Search: 364/200, 364/900, 364/706
• US Class Current: 711/163
• CPC Class Codes: G06F 12/1433 for a module or a part of a module

Abstract

A digital processing device fabricated on a single semiconductor substrate includes an electrically programmable memory, a random access memory, a central processing unit, all connected by an information transfer bus. An external interface is provided connected to the information transfer bus to provide information contained on the bus to external devices. At least one security bit is provided to determine the status of data stored in the nonvolatile memory and portions of the random access memory. An external interface inhibit circuit is connected to the external interface. Address logic is connected to the information transfer bus to determine when information contained in the electrically programmable memory or the random access memory is being accessed. The address logic also determines the security status of information stored in the selected portions of the random access memory and the electrically programmable memory. In addition, the address logic is connected to the central processing unit to determine when an instruction operand is being fetched. The address logic is also connected to the external interface inhibit circuit to inhibit the operation of the external interface when an instruction operand is being fetched from the electrically programmable memory or selected portions of the random access memory.

Claims

1. A data processing device formed on a single semiconductor substrate comprising:

a central processing means for performing data processing operations upon data in accordance with instructions, said data processing operations including at least one memory access operation for recall of data or an instruction stored in a specified address location;

a nonvolatile memory means having a plurality of address locations which are a first subset of the possible address locations of said at least one memory access operation, for storing data and instructions which define data processing operations at respective address locations;

a temporary read-write memory means having a plurality of address locations which are a second subset of the possible address locations, said second subset including a secure set of address locations, for temporarily storing data and instructions which define data processing operations at respective address locations;

an information transfer means connected to said central processing means, said nonvolatile memory means and said temporary read-write memory means for transfer of data and instructions;

an external interface means connected to said information transfer means for providing information to at least one device external to said single semiconductor substrate;

at least one security bit memory means disposed in proximity to said nonvolatile memory means, each for storing therein a single bit of data indicating a secure state when said nonvolatile memory means and said secure subset of memory locations of said temporary read-write memory means is to be secure or a nonsecure state;

address logic means connected to said central processing means, said information transfer means and said at least one security bit memory means for generating a security signal when said security bit memory means indicates a secure state and said central processing means is performing a data processing operation in accordance with an instruction including a memory access operation to recall data as an operand which is stored in either said nonvolatile memory means and or in said secure set of address locations of said temporary read-write memory means; and

an external interface inhibit means connected to said external interface means and said address logic means for inhibiting the transfer of data and instructions to the external device via said external interface means upon reception of said security signal.

2. A data processing device according to claim 1, wherein said at least one security bit memory means is programmable.

3. A data processing device according to claim 2, wherein said address logic does not generate said security signal when said central processing means is performing a data processing operation in accordance with an instruction including a memory access operation to recall data as an operand which is stored in an address location within said second subset of address locations but not included in said secure set of address locations, whereby said data may be accessed by said at least one external device via said external interface means.