Digital private branch exchange

• US 4,521,879 A
• Filed: 08/04/1981
• Issued: 06/04/1985
• Est. Priority Date: 11/25/1977
• Status: Expired due to Term

• Current Assignee: Shared Technologies Allegiance, Inc.
• Original Assignee: United Technologies Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Breidenstein, Charles J., Gueldenpfennig, Klaus, Oswald, William A., Narula, Karam V., Russell, Stanley L.
• Primary Examiner(s): Brown, Thomas W.
• Application Number:
  US06/289,960
• Time in Patent Office: 1,400 Days
• Field of Search: 179/18 ES, 179/18 BC, 179/18 AD, 370/68, 370/66, 370/58, 370/62, 370/110.1
• US Class Current: 370/267
• CPC Class Codes: G06F 15/16 Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs coordinating program control therefor G06F9/52; in regulating and control system G05B
• CPC Class Codes: H04Q 11/0407 using a stored programme control

Abstract

A digital private automatic branch exchange provides a plurality of ports which may comprise line trunks or operator circuits, the ports being grouped with each group being controlled by an individual microprocessor circuit which performs all real time control over the ports. Voice communication between ports is effected by time division multiplex in connection with a digital switch system forming part of a common control which is controlled by a central processing unit responsive to the microprocessors in each port group for assigning time slots to each interconnection channel. Isolation between the central processing unit and the rest of the system is provided by a peripheral bus to which the common control units and port groups are connected, which peripheral bus is connected to the CPU bus by way of an interface circuit, permitting the system to operate with various types of central processing units without redesign of the peripheral units. A conference circuit is also provided for making available a range of conference sizes by combining the available lines to the conference circuit into groups of a predetermined size which may be expanded by combining groups to form conferences of larger or intermediate size.

Claims

1. An automatic private branch exchange comprising

a plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups;

first stored program control means including a single individual microprocessor unit dedicated to each port for performing all real-time control in connection with the ports of the respective groups;

a common transmission network for all of said port groups including a plurality of inputs and a plurality of outputs and switching means for selectively interconnecting an input to an output;

each port group including information transmission means for connecting the ports to the inputs and outputs of said transmission network; and

second stored program control means including a central processing unit responsive to supervisory information from said first stored program control means for controlling said switching means to interconnect designated ports for establishing a communication path therebetween;

said first stored program control means further including, in each port group, strobe signal generating means responsive to the associated microprocessor unit for generating strobe signals for respective pairs of ports in the port group and port interface means connected to said microprocessor unit for applying said strobe signals to said pairs of ports sequentially in a repetitive cycle to sample the status of said ports.

2. An automatic private branch exchange according to claim 1 wherein said ports of each port group are subdivided into subgroups of common type ports, each subgroup of ports being connected in common to a first sense line for indicating the status of the port upon receipt of a strobe signal and being connected selectively in a predetermined combination to a second sense line for indicating the port type of the subgroup, said sense lines extending to said port interface means.

3. An automatic private branch exchange according to claim 2 wherein each strobe signal is applied on a separate line from said port interface means in common to a pair of ports in different port subgroups.

4. An automatic private branch exchange according to claim 1 wherein said port interface means includes means responsive to said microprocessor unit for applying command signals to said ports to effect control thereover.

5. An automatic private branch exchange according to claim 1, further including timer means connected to said strobe signal generating means for generating a signal to reset said microprocessor unit whenever a preselected strobe signal fails to be generated.

6. An automatic private branch exchange according to claim 1 wherein said first stored program control means further includes, in each port group, status means for transmitting status information regarding said microprocessor unit to said second stored program control means and control means responsive to control pulses from said central processing unit for timing the transmission of status information by said status means or resetting said microprocessor unit.

7. An automatic private branch exchange according to claim 6 wherein said control means includes means responsive to a pulse train to effect said timing or resetting functions in dependence on the pulse duration thereof.

8. An automatic private branch exchange according to claim 7 wherein said control means includes first means responsive to a pulse from said central processing unit for applying a load signal to said status means to enable transmission of status information to said second stored program control means, second means responsive to said pulse for inhibiting said first means, and third means responsive to the duration of said pulse for disabling said second means upon detection of a first duration and for generating a reset pulse upon detection of a second duration longer than said first duration.

9. An automatic private branch exchange according to claim 1 wherein said information transmission means comprises means for multiplexing communication signals from said ports onto a signal communication channel for application to said ports.

10. An automatic private branch exchange according to claim 9 wherein said transmission network comprises an asynchronous time slot interchange system.

11. An automatic private branch exchange according to claim 10 wherein each port further includes means for converting communication signals from said ports to digital form prior to application to said multiplexing means.

12. An automatic private branch exchange comprising

a plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups;

a group of service circuits separate from said port groups and including dial tone senders and detectors;

stored program control means including an individual microprocessor unit dedicated to each port group and said service circuit group for performing supervisory control in connection with the ports and service circuits of said groups; and

common control means connected to said ports and service circuits including a transmission switching network and a central processing unit of the stored program type responsive to supervisory information from said stored program control means for controlling said transmission switching network to connect a given port to a service circuit or another designated port, further including an operator console comprising a plurality of actuatable keys, signal generating means responsive to actuation of one or more of said keys for generating respective key transition signals, multiplexing means for multiplexing said key transition signals, and a data link for transmitting said multiplexed key transition signals to said common control means.

13. An automatic private branch exchange according to claim 12, wherein said common control means further includes memory means for storing the functional identification of said actuatable keys for use by said central processing unit in controlling said transmission switching network.

14. An automatic private branch exchange according to claim 13, wherein said operator console further comprises visual indicator means for indicating the operating condition of selected ones of said keys, and decoding means responsive to selected control signals received on said data link from said common control means for selectively energizing said visual indicator means.

15. An automatic private branch exchange according to claim 12 wherein said common control means further includes a memory dedicated to said central processing unit and storing the functional identification of the keys of said operator console, a first bus connecting said memory to said central processing unit, controller means for controlling said transmission switching network in response to said central processing unit, attendant interface means for connecting said data link from said operator console to said central processing unit, a second bus connected to said controller means and said attendant interface means, and interrupt control means for connecting said first bus to said second bus.

16. An automatic private branch exchange according to claim 12 wherein said stored program control means further includes, in each port group, status means for transmission of status information regarding said microprocessor unit to said common control means, and control means responsive to control pulses from said central processing unit for timing the transmission of status information by said status means or resetting said microprocessor unit.

17. An automatic private branch exchange according to claim 16 wherein said control means is responsive to a pulse train to effect said timing or resetting functions in dependence on the pulse duration thereof.

18. An automatic private branch exchange according to claim 15 further including processor interface means for connecting said stored program control means to said second bus.

19. An automatic private branch exchange according to claim 18 wherein said interrupt control means comprises decoder mens for decoding address signals received from said central processing unit which identify one of the means connected to said second bus and enable means responsive to said decoder means for applying an enable signal on said second bus to enable said identified one of said means to communicate with said central processing unit via said second bus, said interrupt control means and said first bus.

20. An automatic private branch exchange according to claim 19 wherein each of said means connected to said second bus include request means for generating an interrupt signal when said means requires connection to said central processing unit and means for applying said interrupt signal on said second bus to said interrupt control means.

21. An automatic private branch exchange according to claim 20 wherein said interrupt control means further comprises storage means for storing interrupt signals received on said second bus, priority determining means for selecting stored interrupt signals on the basis of a predetermined priority and vector generating means for applying a vector signal on said first bus designating an interrupt signal selected by said priority determining means.

22. An automatic private branch exchange according to claim 21 wherein said interrupt control means further comprises masking means responsive to signals from said central processing unit on said first bus for inhibiting storage of selected interrupt signals by said storage means.

23. An information handling system comprising

a plurality of information ports between which information is to be transferred;

stored program control means for performing supervisory control in connection with said ports;

transmission interconnection means for selectively interconnecting ports on the basis of supervisory information from said stored program control means; and

common control means for controlling said transmission interconnection means including a central processing unit of the stored program type, a memory dedicated to said central processing unit, input/output means for directly communicating with said central processing unit, a first bus connecting said memory and said input/output means to said central processing unit, interface circuit means for connecting said stored program control means to said central processing unit, controller means for controlling said transmission interconnection means in response to said central processing unit, a second bus connected to said interface circuit means and said controller means, and interrupt control means for connecting said first bus to said second bus for interfacing said central processing unit with the means connected to said second bus so that said interface circuit means and said controller means may effectively operate with different types of central processing units.

24. An information switching system according to claim 23 further including processor interface means for connecting said stored program control means to said second bus.

25. An information handling system according to claim 24 wherein said interrupt control means comprises decoder means for decoding address signals received from said central processing unit which identify one of the means connected to said second bus and enable means responsive to said decoder means for applying an enable signal on said second bus to enable said identified one of said means to communicate with said central processing unit via said second bus, said interrupt control means and said first bus.

26. An information handling system according to claim 25 wherein each of said means connected to said second bus includes request means for generating an interrupt signal when said means requires connection to said central processing unit and means for applying said interrupt signal on said second bus to said interrupt control means.

27. An information handling system according to claim 26 wherein said interrupt control means further comprises storage means for storing interrupt signals received on said second bus, priority determining means for selecting stored interrupt signals on the basis of a predetermined priority and vector generating means for applying a vector signal on said first bus designating an interrupt signal selected by said priority determining means.

28. An information handling system according to claim 27 wherein said interrupt control means further comprises masking means responsive to signals from said central processing unit on said first bus for inhibiting storage of selected interrupt signals by said storage means.

29. An information handling system according to claim 25 further including an operator complex comprising a console having a plurality of actuatable keys each having first and second operative states, means for generating key state signals indicating the operative state of each of said keys, means for sequentially multiplexing said key state signals, and message formulating means for formulating messages to be sent to said common control including key state and key identification information.

30. An information handling system according to claim 29 further including attendant interface means connected to said second bus for applying to said second bus said messages from said message formulating means.

31. An information handling system according to claim 30 wherein the functional identification of said actuatable keys is stored in said memory dedicated to said central processing unit.

32. A digital information handling system comprising:

a plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups;

data conversion means in each port group for converting data transmitted from and to the ports thereof from analog-to-digital and digital-to-analog form, respectively;

multiplexing-demultiplexing means in each port group for multiplexing the data derived from said ports through said data conversion means onto a single information channel and for demultiplexing data received from said information channel to be applied to said data conversion means; and

common control means including a digital transmission network connected to the information channels of each port group for interconnecting ports through said digital transmission network by asynchronous time slot interchange, a central processing unit responsive to supervisory information received from said ports and a memory dedicated to said central processing unit for storing a program to effect said time slot interchange of data through said digital transmission network, said digital transmission network including data conditioner means for multiplexing the multiplexed data received on the information channels from each port group and for demultiplexing the data to be applied to the respective information channels, and matrix switch means connected to said data conditioner means and responsive to said central processing unit for effecting time slot interchange of the data obtained from said data conditioner means, said matrix switch means including a plurality of matrix switches each including a send memory, a receive memory and control means for shifting data into said send memory and out of said receive memory during one portion of a clock cycle and for shifting data from a send memory to a receive memory during another portion of said clock cycle, wherein said digital transmission network further includes an expander/concentrator network interconnecting the send and receive memories of each of said matrix switches.

34. A digital information handling system according to claim 32, wherein said common control means further includes a memory dedicated to said central processing unit for storing a program to effect time slot interchange of data through said digital transmission network, a first bus connecting said memory to said central processing unit, controller means for controlling said matrix switch means in response to control signals from said central processing unit, a second bus connected to said controller means, and interrupt control means for connecting said first bus to said second bus.

35. A digital information handling system according to claim 34, further including stored program control means including an individual microprocessor unit dedicated to each port group for performing all supervisory control in connection with the ports of the respective groups.

36. A digital information handling system according to claim 35, further including processor interface means for connecting said stored program control means to said second bus.

37. A digital information handling system according to claim 36 wherein said interrupt control means comprises decoder means for decoding address signals received from said central processing unit which identify one of the means connected to said second bus and enable means responsive to said decoder means for applying an enable signal on said second bus to enable said identified one of said means to communicate with said central processing unit via said second bus, said interrupt control means and said first bus.

38. A digital information handling system according to claim 37 wherein each of said means connected to said second bus includes request means for generating an interrupt signal when said means requires connection to said central processing unit and means for applying said interrupt signal on said second bus to said interrupt control means.

39. A digital information handling system according to claim 38 wherein said interrupt control means further comprises storage means for storing interrupt signals received on said second bus, priority determining means for selecting stored interrupt signals on the basis of a predetermined priority and vector generating means for applying a vector signal on said first bus designating an interrupt signal selected by said priority determining means.

40. A digital information handling system according to claim 39 wherein said interrupt control means further comprises masking means responsive to signals from said central processing unit on said first bus for inhibiting storage of selected interrupt signals by said storage means.

41. A digital information handling system according to claim 40, further including an operator complex comprising a console having a plurality of actuatable keys each having first and second operative states, means for generating key state signals indicating the operative state of each of said keys, means for sequentially multiplexing said key state signals, and message formulating means for formulating messages to be sent to said common control means including key state and key identification information.

42. A digital information handling system according to claim 41, further including attendant interface means connected to said second bus for applying to said second bus said messages from said message formulating means.

43. A digital information handling system according to claim 42 wherein the functional identification of said actuatable keys is stored in said memory dedicated to said central processing unit.

33. A digital information handling system comprising:

a plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups;

data conversion means in each port group for converting data transmitted from and to the ports thereof from analog-to-digital and digital-to-analog form, respectively;

multiplexing-demultiplexing means in each port group for multiplexing the data derived from said ports through said data conversion means onto a single information channel and for demultiplexing data received from said information channel to be applied to said data conversion means; and

common control means including a digital transmission network connected to the information channels of each port group for interconnecting ports through said digital transmission network by asynchronous time slot interchange, a central processing unit responsive to supervisory information received from said ports and a memory dedicated to said central processing unit for storing a program to effect said time slot interchange of data through said digital transmission network, said digital transmission network including data conditioner means for multiplexing the multiplexed data received on the information channels from each port group and for demultiplexing the data to be applied to the respective information channels, and matrix switch means connected to said data conditioner means and responsive to said central processing unit for effecting time slot interchange of the data obained from said data conditioner means, wherein said data conditioner means includes first means connected to receive the information from said port groups for converting the serial data of each channel to parallel form and second means connected to the output of said first means for converting the parallel data from said first means to serial form on plural output leads to said matrix switch means.

44. A digital communication switching system comprising a plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups;

stored program control means including an individual microprocessor unit dedicated to each port group for performing supervisory control in connection with the ports of the respective groups;

data conversion means for pulse code modulating and demodulating data received from and applied to said ports in each port group;

common control means including a digital transmission network connected to the data conversion means in each port group and a central processing unit responsive to supervisory information received from said ports for controlling said digital transmission network to interconnect selected ports by asychronous time slot interchange; and

a conference circuit connected to said digital transmission network by way of a preselected number of data highways for establishing one or more conference connections each including three or more ports, including means for summing the digital contents of selected data channels to produce group conference signals.

45. A digital communication switching system according to claim 44 wherein said conference circuit comprises means for receiving sequential data channels of information from said digital transmission network on said data highways, a random access memory connected to said receiving means for storing the contents of a predetermined number of said data channels, master counter means for producing a plurality of clock signals, arithmetic means responsive to said clock signals for summing the contents of said data channels stored in said memory in preselected conference groups to produce group total signals and for successively subtracting from said group total signals the contents of said data channels of the group to produce a plurality of group conference channels, and means for transmitting said group conference channels sequentially to said digital transmission network on said data highways.

46. A digital communication switching system according to claim 45, wherein said common control means includes means in combination with said central processing unit for interconnecting one data channel of a pair of conference groups by time slot interchange in said digital transmission network to create an expanded conference group.