Digital private branch exchange
First Claim
1. An automatic private branch exchange comprisinga plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups;
- first stored program control means including a single individual microprocessor unit dedicated to each port for performing all real-time control in connection with the ports of the respective groups;
a common transmission network for all of said port groups including a plurality of inputs and a plurality of outputs and switching means for selectively interconnecting an input to an output;
each port group including information transmission means for connecting the ports to the inputs and outputs of said transmission network; and
second stored program control means including a central processing unit responsive to supervisory information from said first stored program control means for controlling said switching means to interconnect designated ports for establishing a communication path therebetween;
said first stored program control means further including, in each port group, strobe signal generating means responsive to the associated microprocessor unit for generating strobe signals for respective pairs of ports in the port group and port interface means connected to said microprocessor unit for applying said strobe signals to said pairs of ports sequentially in a repetitive cycle to sample the status of said ports.
11 Assignments
0 Petitions
Accused Products
Abstract
A digital private automatic branch exchange provides a plurality of ports which may comprise line trunks or operator circuits, the ports being grouped with each group being controlled by an individual microprocessor circuit which performs all real time control over the ports. Voice communication between ports is effected by time division multiplex in connection with a digital switch system forming part of a common control which is controlled by a central processing unit responsive to the microprocessors in each port group for assigning time slots to each interconnection channel. Isolation between the central processing unit and the rest of the system is provided by a peripheral bus to which the common control units and port groups are connected, which peripheral bus is connected to the CPU bus by way of an interface circuit, permitting the system to operate with various types of central processing units without redesign of the peripheral units. A conference circuit is also provided for making available a range of conference sizes by combining the available lines to the conference circuit into groups of a predetermined size which may be expanded by combining groups to form conferences of larger or intermediate size.
-
Citations
46 Claims
-
1. An automatic private branch exchange comprising
a plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups; -
first stored program control means including a single individual microprocessor unit dedicated to each port for performing all real-time control in connection with the ports of the respective groups; a common transmission network for all of said port groups including a plurality of inputs and a plurality of outputs and switching means for selectively interconnecting an input to an output; each port group including information transmission means for connecting the ports to the inputs and outputs of said transmission network; and second stored program control means including a central processing unit responsive to supervisory information from said first stored program control means for controlling said switching means to interconnect designated ports for establishing a communication path therebetween; said first stored program control means further including, in each port group, strobe signal generating means responsive to the associated microprocessor unit for generating strobe signals for respective pairs of ports in the port group and port interface means connected to said microprocessor unit for applying said strobe signals to said pairs of ports sequentially in a repetitive cycle to sample the status of said ports. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. An automatic private branch exchange comprising
a plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups; -
a group of service circuits separate from said port groups and including dial tone senders and detectors; stored program control means including an individual microprocessor unit dedicated to each port group and said service circuit group for performing supervisory control in connection with the ports and service circuits of said groups; and common control means connected to said ports and service circuits including a transmission switching network and a central processing unit of the stored program type responsive to supervisory information from said stored program control means for controlling said transmission switching network to connect a given port to a service circuit or another designated port, further including an operator console comprising a plurality of actuatable keys, signal generating means responsive to actuation of one or more of said keys for generating respective key transition signals, multiplexing means for multiplexing said key transition signals, and a data link for transmitting said multiplexed key transition signals to said common control means. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
-
-
23. An information handling system comprising
a plurality of information ports between which information is to be transferred; -
stored program control means for performing supervisory control in connection with said ports; transmission interconnection means for selectively interconnecting ports on the basis of supervisory information from said stored program control means; and common control means for controlling said transmission interconnection means including a central processing unit of the stored program type, a memory dedicated to said central processing unit, input/output means for directly communicating with said central processing unit, a first bus connecting said memory and said input/output means to said central processing unit, interface circuit means for connecting said stored program control means to said central processing unit, controller means for controlling said transmission interconnection means in response to said central processing unit, a second bus connected to said interface circuit means and said controller means, and interrupt control means for connecting said first bus to said second bus for interfacing said central processing unit with the means connected to said second bus so that said interface circuit means and said controller means may effectively operate with different types of central processing units. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
-
-
32. A digital information handling system comprising:
-
a plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups; data conversion means in each port group for converting data transmitted from and to the ports thereof from analog-to-digital and digital-to-analog form, respectively; multiplexing-demultiplexing means in each port group for multiplexing the data derived from said ports through said data conversion means onto a single information channel and for demultiplexing data received from said information channel to be applied to said data conversion means; and common control means including a digital transmission network connected to the information channels of each port group for interconnecting ports through said digital transmission network by asynchronous time slot interchange, a central processing unit responsive to supervisory information received from said ports and a memory dedicated to said central processing unit for storing a program to effect said time slot interchange of data through said digital transmission network, said digital transmission network including data conditioner means for multiplexing the multiplexed data received on the information channels from each port group and for demultiplexing the data to be applied to the respective information channels, and matrix switch means connected to said data conditioner means and responsive to said central processing unit for effecting time slot interchange of the data obtained from said data conditioner means, said matrix switch means including a plurality of matrix switches each including a send memory, a receive memory and control means for shifting data into said send memory and out of said receive memory during one portion of a clock cycle and for shifting data from a send memory to a receive memory during another portion of said clock cycle, wherein said digital transmission network further includes an expander/concentrator network interconnecting the send and receive memories of each of said matrix switches. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
-
-
33. A digital information handling system comprising:
-
a plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups; data conversion means in each port group for converting data transmitted from and to the ports thereof from analog-to-digital and digital-to-analog form, respectively; multiplexing-demultiplexing means in each port group for multiplexing the data derived from said ports through said data conversion means onto a single information channel and for demultiplexing data received from said information channel to be applied to said data conversion means; and common control means including a digital transmission network connected to the information channels of each port group for interconnecting ports through said digital transmission network by asynchronous time slot interchange, a central processing unit responsive to supervisory information received from said ports and a memory dedicated to said central processing unit for storing a program to effect said time slot interchange of data through said digital transmission network, said digital transmission network including data conditioner means for multiplexing the multiplexed data received on the information channels from each port group and for demultiplexing the data to be applied to the respective information channels, and matrix switch means connected to said data conditioner means and responsive to said central processing unit for effecting time slot interchange of the data obained from said data conditioner means, wherein said data conditioner means includes first means connected to receive the information from said port groups for converting the serial data of each channel to parallel form and second means connected to the output of said first means for converting the parallel data from said first means to serial form on plural output leads to said matrix switch means.
-
-
44. A digital communication switching system comprising a plurality of ports including line circuits and trunk circuits, said ports being divided into a plurality of distinct groups;
-
stored program control means including an individual microprocessor unit dedicated to each port group for performing supervisory control in connection with the ports of the respective groups; data conversion means for pulse code modulating and demodulating data received from and applied to said ports in each port group; common control means including a digital transmission network connected to the data conversion means in each port group and a central processing unit responsive to supervisory information received from said ports for controlling said digital transmission network to interconnect selected ports by asychronous time slot interchange; and a conference circuit connected to said digital transmission network by way of a preselected number of data highways for establishing one or more conference connections each including three or more ports, including means for summing the digital contents of selected data channels to produce group conference signals. - View Dependent Claims (45, 46)
-
Specification