Battery saving frequency synthesizer arrangement

• US 4,521,918 A
• Filed: 11/10/1980
• Issued: 06/04/1985
• Est. Priority Date: 11/10/1980
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: General Electric Company
• Inventors: Challen, Richard F.
• Primary Examiner(s): Chin, Tommy P.
• Application Number:
  US06/205,516
• Time in Patent Office: 1,667 Days
• Field of Search: 455/119, 455/125, 455/127, 455/165, 455/183, 455/185, 455/117, 455/75, 455/76, 455/217, 455/343, 331/1 A, 331/10, 331/11, 331/14, 331/16, 331/17, 331/18, 331/25, 331/23, 331/30, 331/34, 332/19, 330/9, 358/191.1, 358/195.1
• US Class Current: 455/343.1
• CPC Class Codes: H03L 2207/08 Modifications of the phase-locked loop for ensuring constant frequency when the power supply fails or is interrupted, e.g. for saving power
• CPC Class Codes: H03L 7/145 the switched reference signal being derived from the controlled oscillator output signal
• CPC Class Codes: H04W 52/0209 in terminal devices terminal devices per se H04W88/02
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

An arrangement for reducing the amount of battery supplied power to a high frequency synthesizer. The phase-locked loop section of the synthesizer is periodically disconnected from the battery supplied power. In order to prevent substantial drift of the phase-locked loop during such power interruption, a control signal is provided for maintaining the VCO frequency. By minimizing the frequency drift, the loop can be re-locked in a short period of time following each power interruption.

Claims

1. A frequency synthesizer circuit comprising:

a voltage controlled oscillator (VCO) having a control input;

an integrator having an output coupled to said VCO control input and an input;

phase-locked loop (PLL) synthesizer means for comparing a signal output of said VCO with a signal from a reference oscillator and (b) providing a loop control signal related thereto;

means for applying and interrupting power to the PLL synthesizer means;

switch means for selectively coupling the input of the integrator to either (a) the loop control signal from the PLL synthesizer means when power is applied thereto or (b) a receiver discriminator signal derived from a discriminator separate and distinct from said PLL synthesized means when power to the PLL synthesizer means is interrupted, whereby the frequency of the VCO is controlled by the receiver discriminator signal during periods of power interruption to the PLL synthesizer means.

2. A method for frequency synthesizing comprising the steps of:

generating with phase-locked loop means, a loop control signal for use in controlling a voltage controlled oscillator having a control signal input;

coupling the control signal input of the VCO to the loop control signal of the PLL means;

locking the PLL means;

decoupling the control signal input of the VCO from the loop control signal of the PLL means and coupling it instead to the output of a receiver discriminator separate and distinct from the PLL means so that the VCO will be controlled by the discriminator output rather than by the loop control signal from the PLL means, and

interrupting power to the phase-locked loop means simultaneously with the decoupling of said loop control signal to the VCO.

3. A method for operating radio communications equipment having a hook switch and a phase-locked loop (PLL) synthesizer including phase-locked loop (PLL) means for generating a loop control signal, a voltage controlled oscillator (VCO) having a control input, and an integrator circuit coupled to the VCO control input, comprising the steps of:

(a) locking the PLL means and coupling the integrator circuit thereto for deriving the loop control signal from the PLL means;

(b) interrupting power to the PLL means, decoupling the integrator circuit from said PLL means, and coupling the integrator circuit to another source of control signal separate and distinct from the PLL means;

(c) applying power to the PLL means and coupling the integrator circuit thereto for deriving the loop control signal from the PLL means in response to any of the following;

(aa) a received command to switch frequency from a current frequency being synthesized by said synthesizer to a new frequency and to transmit on the new frequency, or

(bb) a received command to transmit on the current frequency, or

(cc) an off-hook condition of said hook switch, or

(dd) loss of a received signal;

(d) and returning to step (b) in the absence of any one of the conditions (aa)-(dd) of step (c).

4. A method for operating radio communications equipment having a hook switch and a phase-locked loop (PLL) synthesizer including phase-locked loop (PLL) means and a voltage controlled oscillator (VCO) wherein the equipment includes a receiving section having a discriminator separate and distinct from the PLL means, comprising the steps of:

(a) locking the PLL means to provide a loop control signal to the VCO;

(b) synchronously interrupting power to the PLL means, decoupling said PLL means from the VCO, and coupling a signal from the discriminator to the control input of the VCO to control its frequency;

(c) enabling the PLL means continuously in response to the occurrence of any of the following conditions;

(aa) a received command calling for a switch in frequency from a current frequency being synthesized by said synthesizer to a new frequency and transmission on the new frequency,

(bb) a received command calling for transmission on the current frequency,

(cc) an off-hook condition of said hook switch, or

(dd) loss of a received signal, and

(d) returning to the PLL means to a disabled state wherein the output of the discriminator drives the VCO in response to the absence of any of the conditions (aa) through (dd) above.