Digital processor for use with an accelerometer based angular rate sensor

• US 4,522,062 A
• Filed: 09/02/1983
• Issued: 06/11/1985
• Est. Priority Date: 09/02/1983
• Status: Expired due to Term

• Current Assignee: Alliedsignal Inc.
• Original Assignee: Sundstrand Data Control, Inc.
• Inventors: Peters, Rex B.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/528,775
• Time in Patent Office: 648 Days
• Field of Search: 73/505, 73/510, 73/517 R, 73/517 B
• US Class Current: 73/504.04
• CPC Class Codes: G01C 19/5705 using masses driven in reciprocating rotary motion about an axis
• CPC Class Codes: G01C 19/5776 Signal processing not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719

Abstract

In a structure utilizing a pair of accelerometers vibrating in a direction normal to their force sensing axes, a circuit utilizing voltage-to-frequency converters is utilized to convert the analog output signals from the accelerometers to digital signals representing the translational motion and the angular rate rotation of the structure.

Claims

1. A circuit for deriving from an acceleration signal produced by an accelerometer moving with a periodic frequency ω

an angular rate signal, comprising;

sign switching means operatively connected to the accelerometer for multiplying the acceleration signal by a zero mean periodic function of frequency ω

;

first conversion means operatively connected to said signal switching means for converting said multiplied acceleration signal to a first frequency e signal;

first counter means operatively connected to said first conversion means for generating a digital angular rate signal in response to said first frequency signal wherein said counter means includes a counter circuit responsive to the frequency ω

for counting cycles of said first frequency signal over a complete cycle of said frequency ω

.

2. The circuit of claim 1 wherein said first conversion means includes a voltage to frequency converter circuit.

3. The circuit of claim 1 additionally including:

second conversion means operatively connected to the accelerometer for converting said acceleration signal to a second frequency signal; and

second counter means operatively connected to said second conversion means for generating a digital force signal in response to said second frequency signal.

4. The circuit of claim 3 wherein:

said first conversion means includes a voltage to frequency converter circuit;

said second conversion means includes a second voltage to frequency converter circuit; and

said second counter means including a second counter circuit responsive to the frequency ω

for counting cycles of said second frequency signal over a complete cycle of the frequency ω

.

5. A circuit for deriving from a pair of accelerometers which are being vibrated in a direction substantially normal to their force sensing axes at a frequency ω

an angular rate signal representing the angular rate of rotation of the accelerometers, comprising;

sign switching means operatively connected to the accelerometers for multiplying the acceleration signals from the accelerometers by a zero mean periodic function of ω

;

first conversion means operatively connected to said sign switching means for converting said multiplied acceleration signals to a first frequency signal; and

first counter means operatively connected to said first conversion means for generating from said first frequency signal a digital angular rate signal representing the rate of rotation of the accelerometers.

6. The circuit of claim 5 additionally including pre-separation means operatively connected between the accelerometers and said signal switching means for substantially removing force components from the acceleration signals.

7. The circuit of claim 5 additionally including:

second conversion means operatively connected to the accelerometers for converting the accelerometer signals into second frequency signals; and

second counter means operatively connected to said second conversion means for generating from said second frequency signal a digital force signal.

8. The circuit of claim 7 additionally including pre-separation means operatively connected between the accelerometers and said signal switching means as well as said second conversion means for removing force components from the acceleration signals applied to said sign switching means and for removing angular rotation, components from the acceleration signals applied to said second conversion means.

9. The circuit of claim 8 wherein the accelerometers are aligned with their force sensing axes in the same direction said pre-seperation means includes means for summing said acceleration signals applied to said second conversion means and for differencing said acceleration signals applied to said sign switching means.

10. The circuit of claim 8 wherein the accelerometers are aligned with their force sensing axes in opposite directions said pre-seperation means includes means for differencing said acceleration signals applied to said second conversion means and for summing said acceleration signals applied to said signal switching means.

11. The circuit of claim 8 wherein both said first and said second counter means includes counter circuits responsive to the frequency ω

to accumulate digital count signals that represent the number of cycles of said first and second frequencies for a predetermined portion of a cycle of the ω

frequency.

12. The circuit of claim 11 additionally including correction means operatively connected to said first and said second counter means for combining the output e₁₁ of said first counter circuit with the output e₂₁ of said second counter circuit along with values representing the scale factors K₁ and K₂ of the accelerometers for a first one of said predetermined ω

cycle portions and combining the output of said first counter circuit e₁₂ with the output of said second counter circuit e₂₂ along with said scale factor values over a second one of said predetermined ω

cycle portions to generate said digital angular rate signal.

13. The circuit of claim 12 wherein said first one of said predetermined ω

cycle portions is a first one half of an ω

cycle wherein said zero mean periodic function equals +1 and said second one of said predetermined ω

cycle portions is a second one half of an ω

cycle wherein said zero mean periodic function equals -1.

14. The circuit of claim 13 wherein said correction means produces said digital angular rate signal Δ

θ

according to the relation;

##EQU2## where in each counter circuit output term e_ij i= 1 represents said second counter circuit,

i=2 represents said first counter circuit,

j=1 represents said first one half of an ω

cycle, and

j=2 represents said second one half of an ω

cycle.

15. The circuit of claim 14 wherein said correction means also includes means for combining the outputs of said first and second counter circuits to generate said digital force signal Δ

v according to the relation;

##EQU3##

16. A circuit for deriving from acceleration signals produced by a first and a second accelerometer which are being vibrated at a frequency ω

within a frame of reference in a direction normal to their sensitive axis a force signal representing acceleration of the frame of reference along the sensitive axis and an angular rotation signal representing the angular rotation of the frame of reference about an axis normal to the direction of vibration comprising;

a pulse generator circuit for generating pulses having a frequency functionally related to the frequency ω

;

a preprocessor circuit operatively connected to both of the accelerometers including a first summing circuit for combining the acceleration signals into an analog force signal substantially without components representing angular rotation and a second summing circuit for combining the acceleration signals into an analog rate signal substantially without components representing force;

a sign switching circuit connected to said pulse generating circuit said second summing circuit for multiplying said analog rate signal by the zero mean function signal sgncosω

t;

a first voltage to frequency converter circuit connected to said first summing circuit for converting said analog force signal into a first frequency signal;

a second voltage to frequency converter circuit connected to said sign switching circuit for converting said multiplied analog rate signal to a second frequency signal;

a first counter circuit connected to said pulse generator circuit for said first voltage to frequency circuit for counting the cycles of said first frequency signal over a predetermined portion of frequency ω

to generate a digital force signal; and

a second counter circuit connected to said pulse generator circuit and said second voltage to frequency circuit for counting the cycles of said second frequency signal over said predetermined portion of frequency ω

to generate a digital rate signal.

17. The circuit of claim 16 additionally including a correction circuit including:

a circuit to combine said digital force signal with said digital rate signal to generate a corrected force signal Δ

v according to the relation;

##EQU4## and;

a circuit to combine said digital force signal with said digital rate signal to generate a corrected rate signal according to the relation;

##EQU5## where K₁ and K₂ represent the scale factors of the accelerometers and eij represents the outputs of said first and second counter circuits where i denotes the individual counter circuit and j=1 denotes the first half cycle of ω and

j=2 denotes the second half cycle of ω

.