Software protection method and apparatus
First Claim
1. In a computer having a processor unit, a memory and a bus for interfacing said processor unit and said memory, said processor unit being operative to fetch instructions and access data stored in said memory, an apparatus for protecting data stored in said memory, comprising means for applying a "read data" instruction to said processor unit, memory access means for detecting a memory access signal generated by said processor unit to access data stored in said memory in response to said instruction, monitoring means for determining whether said instruction was previously fetched from said memory and means responsive to said memory access means and said monitoring means for enabling memory access only if said instruction was previously fetched from said memory.
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Accused Products
Abstract
In a microprocessor system, data stored in a protected memory (12) within the same housing as the microprocessor (10) are secured by enabling access to the contents of the memory in response to an instruction only if the instruction was previously fetched from the memory (12). Protection circuitry (14) comprises a decoder (22, 24) responsive to the output of a status register in the microprocessor to operate a status signal when the microprocessor is in an instruction fetch machine cycle. The status signal is stored (26) until the protected memory (12) is selected by the microprocessor (10). Access to data in the protected memory (12) is enabled only if the status signal is stored during memory select or the microprocessor is in an I/O machine cycle for communication with a peripheral. In addition, voltage controlled switches within the housing place the bus in a HALT state during memory select unless the microprocessor is in an I/O machine cycle. The protection circuitry (14) is disabled by a fuse (36) within the housing for memory content verification. Following verification, the fuse (36) is blown to secure the memory (12).
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Citations
14 Claims
- 1. In a computer having a processor unit, a memory and a bus for interfacing said processor unit and said memory, said processor unit being operative to fetch instructions and access data stored in said memory, an apparatus for protecting data stored in said memory, comprising means for applying a "read data" instruction to said processor unit, memory access means for detecting a memory access signal generated by said processor unit to access data stored in said memory in response to said instruction, monitoring means for determining whether said instruction was previously fetched from said memory and means responsive to said memory access means and said monitoring means for enabling memory access only if said instruction was previously fetched from said memory.
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2. In a computer having a processor unit, a memory having stored therein instructions and data and a bus for interfacing said processor unit and said memory, said processor unit being operative in a first machine cycle to fetch instructions stored in said memory, at least some of said stored instructions instructing said processor unit to access data stored in said memory, an apparatus for protecting data stored in said memory, comprising monitor means for detecting the first machine cycle of said processor unit and in response generating a status signal to identify machine cycles of said processor unit, means for storing said status signal;
- memory access means for generating a memory access signal for accessing said memory and means responsive to said stored status signal and said memory access signal for enabling access of data stored in said memory only if access of said data is in response to an instruction fetched from said memory.
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3. In a computer having a processor unit, a memory and a bus interfacing said processor unit and said memory, said processor unit being operative in an OP-FETCH machine cycle to fetch an instruction stored in said memory, an apparatus for protecting data stored in said memory, comprising means for monitoring machine cycles of said processor;
- means responsive to said monitoring means for generating an OP-FETCH signal when said processor unit is the OP-FETCH machine cycle, means for storing said OP-FETCH signal until a subsequent machine cycle of said processor, memory access means for generating a memory access signal for memory access in response to a fetch instruction, and means responsive to said OP-FETCH signal and said memory access signal for enabling access of data stored in said memory during said subsequent machine cycle only if said instruction was previously fetched from said memory.
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4. In a computer having a processor unit, a memory having stored therein instructions and data and a bus interfacing said processor unit and said memory, said processor unit being operative in an OP-FETCH machine cycle to fetch an instruction stored in said memory and in a read memory machine cycle for accessing data stored in the memory and having status register means identifying machine cycles of said processor unit;
- an apparatus for protecting contents of said memory, comprising memory access means for generating a memory access signal to access said memory for an operation, monitoring means responsive to said status register means for generating an OP-FETCH signal identifying an OP-FETCH machine cycle of said processor unit, means for storing said OP-FETCH signal and means responsive to said memory select signal and said stored OP-FETCH signal for enabling access of data stored in said memory in response to an instruction only if said instruction was previously fetched from said memory.
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9. In a computer having a processor unit, a memory and a bus interfacing said processor unit and said memory, said processor unit being operative to fetch instructions from said memory and in response to instructions to access data stored in said memory, a method of protecting data stored in said memory, comprising the steps of monitoring status of said processor unit to identify an instruction fetch machine cycle and in response generating a status signal to identify machine cycles of said processor unit;
- storing said status signal;
generating a memory access signal during selection of said memory by said processor unit to perform an operation and responding to said stored status signal and said memory access signal to enable access to data stored in said memory in response to an instruction only if the instruction was previously fetched from said memory. - View Dependent Claims (10, 11, 12, 13)
- storing said status signal;
Specification