Software protection method and apparatus

• US 4,523,271 A
• Filed: 06/22/1982
• Issued: 06/11/1985
• Est. Priority Date: 06/22/1982
• Status: Expired due to Term

• Current Assignee: Raphael L. Levien
• Original Assignee: Raphael L. Levien
• Inventors: Levien, Raphael L.
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Williams, Jr., A. E.
• Application Number:
  US06/390,885
• Time in Patent Office: 1,085 Days
• Field of Search: 364/200, 364/900, 178/22.01, 178/22.09, 178/22.19
• US Class Current: 726/22
• CPC Class Codes: G06F 21/123 by using dedicated hardware, e.g. dongles, smart cards, cryptographic processors, global positioning systems [GPS] devices
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories

Abstract

In a microprocessor system, data stored in a protected memory (12) within the same housing as the microprocessor (10) are secured by enabling access to the contents of the memory in response to an instruction only if the instruction was previously fetched from the memory (12). Protection circuitry (14) comprises a decoder (22, 24) responsive to the output of a status register in the microprocessor to operate a status signal when the microprocessor is in an instruction fetch machine cycle. The status signal is stored (26) until the protected memory (12) is selected by the microprocessor (10). Access to data in the protected memory (12) is enabled only if the status signal is stored during memory select or the microprocessor is in an I/O machine cycle for communication with a peripheral. In addition, voltage controlled switches within the housing place the bus in a HALT state during memory select unless the microprocessor is in an I/O machine cycle. The protection circuitry (14) is disabled by a fuse (36) within the housing for memory content verification. Following verification, the fuse (36) is blown to secure the memory (12).

Claims

1. In a computer having a processor unit, a memory and a bus for interfacing said processor unit and said memory, said processor unit being operative to fetch instructions and access data stored in said memory, an apparatus for protecting data stored in said memory, comprising means for applying a "read data" instruction to said processor unit, memory access means for detecting a memory access signal generated by said processor unit to access data stored in said memory in response to said instruction, monitoring means for determining whether said instruction was previously fetched from said memory and means responsive to said memory access means and said monitoring means for enabling memory access only if said instruction was previously fetched from said memory.

5. The apparatus of any one of claims 1-4, wherein said processor unit includes a microprocessor having a housing and external terminals, said bus being within said housing and coupled to said terminals, and switch means within said bus, said processor unit being further operative in an I/O machine cycle wherein said processor unit communicates through said external terminals to peripheral devices, second means responsive to said monitoring means for identifying an I/O machine cycle and means responsive to said second means and said memory select means for operating said switch means to halt said bus during memory select while said processor unit is in other than an I/O machine cycle.

6. The apparatus of any of claims 1-4, including verification means for controlling said access enabling means to enable verification of contents of said memory.

7. The apparatus of claim 6, wherein said verification means includes fuse means connected in circuit with said bus means, and means for open circuiting said fuse means.

8. The apparatus of any one of claims 1-4, wherein said storing means includes a flip flop.

14. The apparatus of any one of claims 1-4, including logic means for determining whether said processor unit is operating in an I/O cycle, said memory access enabling means being further responsive to said logic means for enabling memory access when said process unit is in an I/O operating cycle.

2. In a computer having a processor unit, a memory having stored therein instructions and data and a bus for interfacing said processor unit and said memory, said processor unit being operative in a first machine cycle to fetch instructions stored in said memory, at least some of said stored instructions instructing said processor unit to access data stored in said memory, an apparatus for protecting data stored in said memory, comprising monitor means for detecting the first machine cycle of said processor unit and in response generating a status signal to identify machine cycles of said processor unit, means for storing said status signal;

memory access means for generating a memory access signal for accessing said memory and means responsive to said stored status signal and said memory access signal for enabling access of data stored in said memory only if access of said data is in response to an instruction fetched from said memory.

3. In a computer having a processor unit, a memory and a bus interfacing said processor unit and said memory, said processor unit being operative in an OP-FETCH machine cycle to fetch an instruction stored in said memory, an apparatus for protecting data stored in said memory, comprising means for monitoring machine cycles of said processor;

means responsive to said monitoring means for generating an OP-FETCH signal when said processor unit is the OP-FETCH machine cycle, means for storing said OP-FETCH signal until a subsequent machine cycle of said processor, memory access means for generating a memory access signal for memory access in response to a fetch instruction, and means responsive to said OP-FETCH signal and said memory access signal for enabling access of data stored in said memory during said subsequent machine cycle only if said instruction was previously fetched from said memory.

4. In a computer having a processor unit, a memory having stored therein instructions and data and a bus interfacing said processor unit and said memory, said processor unit being operative in an OP-FETCH machine cycle to fetch an instruction stored in said memory and in a read memory machine cycle for accessing data stored in the memory and having status register means identifying machine cycles of said processor unit;

an apparatus for protecting contents of said memory, comprising memory access means for generating a memory access signal to access said memory for an operation, monitoring means responsive to said status register means for generating an OP-FETCH signal identifying an OP-FETCH machine cycle of said processor unit, means for storing said OP-FETCH signal and means responsive to said memory select signal and said stored OP-FETCH signal for enabling access of data stored in said memory in response to an instruction only if said instruction was previously fetched from said memory.

9. In a computer having a processor unit, a memory and a bus interfacing said processor unit and said memory, said processor unit being operative to fetch instructions from said memory and in response to instructions to access data stored in said memory, a method of protecting data stored in said memory, comprising the steps of monitoring status of said processor unit to identify an instruction fetch machine cycle and in response generating a status signal to identify machine cycles of said processor unit;

storing said status signal;

generating a memory access signal during selection of said memory by said processor unit to perform an operation and responding to said stored status signal and said memory access signal to enable access to data stored in said memory in response to an instruction only if the instruction was previously fetched from said memory.

10. The method of claim 9, wherein said processor unit includes status register means for identifying machine cycle status, said monitoring step including monitoring signals developed by said status register means.

11. The method of claim 9, including the step of generating an I/O status signal identifying an I/O machine cycle of said processor unit wherein said processor unit is in communication with an external peripheral device on said bus and placing said bus in a HALT state in response to said I/O status signal and said memory access signal during memory access when said processor unit is in other than an I/O machine cycle.

12. The method of claim 11, including the step of verifying contents of said memory by enabling access to data stored in said memory even if the instruction was fetched from other than said memory.

13. The method of claim 12, wherein said verifying step further includes inhibiting placement of the bus in the HALT state.