Associative memory

• US 4,523,301 A
• Filed: 06/01/1983
• Issued: 06/11/1985
• Est. Priority Date: 06/04/1982
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Kadota, Hiroshi, Ichinohe, Eisuke
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US06/499,912
• Time in Patent Office: 741 Days
• Field of Search: 365/49, 365/154, 365/190, 365/202, 365/203
• US Class Current: 365/49.11
• CPC Class Codes: G11C 15/04 using semiconductor elements

Abstract

An associative memory comprises memory cells arrayed in columns and rows, a pair of complementary bit lines disposed for each column of the memory cells, a word line disposed for each row of the memory cells, and a sense line disposed also for each row of the memory cells. Each memory cell includes a bistable circuit provided by a pair of cross-coupled inverters, a pair of first switching elements connected between the two nodal points of the bistable circuit and the bit lines respectively to be controlled depending on the potential of the word line, and a pair of second switching elements and a pair of diodes or like circuit elements having a rectifying characteristic connected in series between the bit lines and the sense line respectively. These second switching elements are controlled depending on the potentials of the two nodal points respectively in the bistable circuit. A load element, a sensing amplifier and a tri-state driver circuit are connected to the sense line. An input reference data bit pattern is applied in complementary fashion to the bit lines, and coincidence or non-coincidence between the input reference data and the stored data is discriminated by checking the output of the sensing amplifier connected to each sense line.

Claims

1. An associative memory comprising memory cells arrayed in columns and rows and each including a bistable circuit having two nodal points having complementary potentials and a pair of first switching elements controlling electrical connections between the nodal points and a pair of bit lines respectively, each of said bit line pairs being disposed for each column of said memory cells, a word line disposed for each row of said memory cells for controlling on-off of said first switching elements depending on its potential, a first series connection of a first rectifying element and a second switching element connected between a sense line and one of said bit lines in each of said memory cells, a second series connection of a second rectifying element and a third switching element connected between said sense line and the other of said bit lines in each of said memory cells, the control terminals of said second and third switching elements being connected to said complementary nodal points respectively in said bistable circuit in each of said memory cells, a sensing amplifier connected to each of said sense lines for sensing the potential thereof, a potential setting circuit connected to each of said sense lines for setting the potential thereof, and a load element connected at one of its terminals to each of said sense lines and at the other terminal to a power source.

2. An associative memory as claimed in claim 1, wherein said rectifying elements in said first and second series connections are replaced by a single rectifying element common to said first and second series connections, and said common element is connected between said sense line and the connection point of said second and third switching elements.

3. An associative memory as claimed in claim 1, wherein an enhancement type field effect transistor is used as each of said first, second and third switching elements, and an enhancement type field effect transistor having its gate and drain connected in common or its gate connected to said sense line is used as each of said rectifying elements.

4. An associative memory as claimed in claim 1, wherein a depletion type field effect transistor having its gate and source connected in common is used as said load element.

5. An associative memory as claimed in claim 1, wherein a dynamic load provided by a field effect transistor having its source connected to said sense line, its drain connected to said power source and its gate connected to a signal source is used as said load element.