Method for manufacturing a semiconductor device

• US 4,523,369 A
• Filed: 09/24/1982
• Issued: 06/18/1985
• Est. Priority Date: 03/31/1982
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Nagakubo, Yoshihide
• Primary Examiner(s): Andrews, Melvyn J.
• Application Number:
  US06/423,107
• Time in Patent Office: 998 Days
• Field of Search: 29/576 W, 29/578, 29/580, 357/49, 357/50, 148/1.5, 148/DIG. 85, 156/643
• US Class Current: 438/433
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/76 Making of isolation regions between components
• CPC Class Codes: H01L 21/762 Dielectric regions , e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
• CPC Class Codes: H01L 21/76237 introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: Y10S 148/085 Isolated-integrated

Abstract

The invention provides a method for manufacturing a semiconductor device, having the steps of: forming a first mask member which has an opening to expose a desired portion of one major surface of a semiconductor substrate; doping an impurity which has the same conductivity type as that of the semiconductor substrate through the opening of the first mask member to form an impurity region of a high concentration in the surface layer of the semiconductor substrate; forming a second mask member on the side surface of the opening of the first mask member while the first mask member is left as it is; forming a groove by selectively etching the semiconductor substrate using the first and second mask members, and at the same time leaving an impurity region of the high concentration at least on the side surface of the groove; and burying an insulating isolation material in the groove.

Claims

1. A method for manufacturing a semiconductor device comprising the steps of (a) forming a first mask member which has an opening to expose a desired portion of a major surface of a semiconductor substrate;

(b) ion-implanting an impurity of the same conductivity type as that of said semiconductor substrate through said opening of said first mask member to form an impurity region of a high concentration in a surface layer of said semiconductor substrate;

(c) substantially forming a second mask member only on a side surface of said opening of said first mask member while said first mask member is left as it is;

(d) forming a groove by selectively etching said semiconductor substrate by using said first and second mask members, while at the same time leaving the impurity region of the high concentration at least on a side surface of said groove; and

(e) burying an insulating isolation member in said groove.

2. The method according to claim 1, in which said step (d) comprises forming said groove such that a bottom thereof reaches the semiconductor substrate through said impurity region of the high concentration.

3. The method according to claim 2, in which said step (d) comprises, after forming said groove, ion-implanting an impurity of the same conductivity type as that of said semiconductor substrate by using said first and second mask members to form an impurity region of a high concentration on that bottom of said groove which is the surface layer of said semiconductor substrate.

4. The method according to claim 1, in which said step (d) comprises forming a groove such that a bottom thereof does not reach the semiconductor substrate with said region of the high concentration left.

5. The method according to claim 1, in which said step (b) comprises forming an impurity region of a high concentration in a surface layer of said semiconductor substrate by an ion-implantation method using an impurity dose of 1×

10¹³ cm^-2 when the impurity concentration of said semiconductor substrate is 3×

10¹³ cm^-3.

6. A method according to claim 1, wherein said first mask member comprises a material selected from the group consisting of silicon dioxide, silicon nitride and aluminum.

7. A method according to claim 1, wherein said second mask member can be etched using said first mask member as a mask.