Method and apparatus for forming hermetically sealed electrical feedthrough conductors

• US 4,525,766 A
• Filed: 01/25/1984
• Issued: 06/25/1985
• Est. Priority Date: 01/25/1984
• Status: Expired due to Fees

• Current Assignee: Concha Corporation
• Original Assignee: Transensory Device Incorporated
• Inventors: Petersen, Kurt E.
• Primary Examiner(s): Griffin, Donald A.
• Application Number:
  US06/573,508
• Time in Patent Office: 517 Days
• Field of Search: 361/283, 427/79, 29/25.41, 29/25.42, 357/51, 174/52 FP
• US Class Current: 361/283.1
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm
• CPC Class Codes: Y10T 29/435 Solid dielectric type

Abstract

Hermetically sealed electrical feedthrough conductors are formed across the periphery or boundary between a hermetically sealed region on a semiconductor substrate and a second or external region thereof by first forming a planar insulative layer on the surface of the silicon substrate along the predetermined path of the feedthrough conductor across the periphery, said insulative layer having at least one planar projection on each side thereof extending out from the path and coming to a point, and then forming thereon a planar metal feedthrough conductor layer that substantially covers the insulative layer, including corresponding metal planar projections. An insulator element sized to encapsulate the region to be sealed is then mallory bonded to the periphery, including the feedthrough conductor, so as to form a hermetic seal along the entire periphery including in the region of said feedthrough conductor. The planar projections form a compression bond that eliminates any tenting region that would otherwise form beneath the insulator element at the edges of the feedthrough conductor and the underlying insulative layer.

Claims

1. A method for forming a hermetically sealed metal feedthrough conductor across the planar surface of a semiconductor substrate, comprising the steps of:

(a) forming a planar insulator layer on said surface along a predetermined path, said insulator layer having at least one planar projection extending out on each side of said path and shaped so as to come to a point;

(b) forming a planar metal feedthrough conductor on the surface of said insulator layer such that the surface of said insulator layer including said projections is at least partially covered by said metal feedthrough conductor, said feedthrough conductor being of a configuration to prevent the formation of a conductive path between said feedthrough conductor and said semiconductor substrate and being proximate said point on said planar projections of said insulator layer to form substantially matching points therewith,

(c) placing the planar surface of an insulator element in contact with said planar semiconductor surface and said metal feedthrough conductor; and

(d) Mallory bonding said insulator element to said semiconductor surface, said points on said planar projections of said insulator layer and said feedthrough conductor causing the formation of a compression bond between said insulator element and said feedthrough conductor and the exposed portions of said insulator layer.

2. The method of claim 1 wherein the step of forming a planar insulator layer comprises the step of forming a layer of silicon dioxide on the surface of said semiconductor substrate having a depth of approximately 0.1 microns, and wherein the step of forming a planar metal feedthrough conductor comprises the step of forming a layer of titanium by deposition of titanium on the surface of said insulator layer and having a depth of approximately 0.1 microns.

3. A method for forming a hermetically sealed feedthrough conductor across a correspondingly sealed boundary area on the surface of a silicon substrate, wherein the seal is formed by electrostatically bonding the surface of a glass substrate to said silicon substrate surface, comprising:

forming an oxide layer on said silicon surface along a predetermined path extending across the boundary area and having at least one planar projection extending out to a point on each side of said oxide layer that is sufficiently sharp so as to create deformation of the glass surface in contact therewith in the area of said projections during bonding;

forming a metal feedthrough conductor layer on the surface of said oxide layer, the edge thereof spaced from the edge of the oxide layer a distance sufficient to prevent a conductive path to be formed between said feedthrough conductor and said silicon surface, said points being proximate said planar projections of said oxide layer so as to form substantially matching points therewith;

placing said glass surface in contact with said silicon surface; and

electrostatically bonding said glass surface to said silicon surface, including forming a compression seal across the exposed surface of said metal conductor during said bonding, a compression seal about said planar projections thereof, and a compression seal about the planar projections of said oxide layer, thereby forming a hermetically sealed boundary area.

4. The method of claim 3 wherein said electrostatic bonding further creates an electrostatic bond between said feedthrough conductor layer and said glass surface.

5. A method for forming a hermetically sealed metal feedthrough conductor in the periphery between first and second regions on a planar silicon substrate, said second region surrounding said first region, comprising the steps of:

(a) forming a planar oxide layer on the surface of said silicon substrate along a predetermined path between said two regions across said periphery, said oxide layer having at least one planar projection extending out on each side of said path and shaped so as to come to a point;

(b) forming a planar metal feedthrough conductor layer on the surface of said oxide layer such that the surface of said oxide layer, including said projections, is substantially covered by said metal feedthrough conductor, said feedthrough conductor being spaced from the edge of said oxide layer to prevent the formation of a conductive path between said feedthrough conductor and said silicon substrate,

(c) placing an insulator element, sized to encapsulate said first region and having a planar surface matching said periphery between said first and second regions, in corresponding contact with said periphery, including contact with said metal feedthrough conductor; and

(d) electrostatically bonding said insulator element to said silicon substrate periphery, by;

(i) heating said insulator element to a point where it is electrically conductive; and

(ii) applying an electrical potential across said insulator element and said silicon substrate while temporarily externally connecting said feedthrough conductor to said silicon substrate, such that said planar insulator element is caused to be attracted into intimate contact with said feedthrough conductor and said periphery progressively so as to close all gaps and form a bond therebetween and a compression seal along the exposed edge of said oxide layer.

6. The method of claim 5 wherein the step of forming a planar oxide layer having at least one planar projection extending out on each side of said path comprises the step of forming each said planar projection along a direction perpendicular to the axis of the path of said oxide layer.

7. The method of claim 6 wherein the step of placing an insulator element in contact with said periphery comprises the step of placing a glass substrate having a polished planar surface in matching contact with said planar periphery.

8. In an integrated circuit device formed on the planar surface of a silicon substrate, a method for forming a hermetically sealed metal feedthrough conductor across the periphery between a first region of said integrated circuit device to be hermetically sealed and a second region of said integrated circuit device, comprising the steps of:

(a) forming a planar oxide layer on the surface of said integrated circuit device along the predetermined path of said metal feedthrough conductor across said periphery, said oxide layer having at least one planar projection extending out on each side of said path and shaped so as to come to a point at its furthest distance from said path;

(b) forming said planar metal feedthrough conductor on the surface of said oxide such that the surface of said oxide including said projections are substantially covered by said metal feedthrough conductor except for a small border along the perimeter of said metal feedthrough conductor of sufficient size to prevent the formation of a conductive path between said feedthrough conductor and said silicon substrate,

(c) placing an insulator element, sized to encapsulate said first region and having a planar surface matching said periphery, in corresponding contact with said periphery, including said metal feedthrough conductor; and

(d) electrostatically bonding said insulator element to said periphery of said integrated circuit device, by;

(i) heating said insulator element to a point where it is electrically conductive; and

(ii) applying an electrical potential of predetermined value across said insulator element and said silicon substrate while temporarily externally connecting said feedthrough conductor to said silicon substrate, thereby causing said planar insulator element to be attracted into intimate contact with said feedthrough conductor and said integrated circuit periphery progressively so as to close all gaps and form a bond therebetween and a compression seal across the exposed border of said oxide layer.

9. The method of claim 8 wherein the step of forming a planar oxide layer having at least one planar projection extending out on each side of the predetermined path of said metal feedthrough conductor includes the step of forming each said planar projection in a direction substantially perpendicular to the path of said feedthrough conductor.

10. The method of claim 8 wherein the step of placing an insulator element in contact with said periphery comprises the step of placing a glass substrate having a polished surface in matching contact with the surface of said periphery.

11. An apparatus for providing a hermetically sealed feedthrough conductor across the planar periphery between a first hermetically sealed region of a semiconductor substrate and a second region of said semiconductor substrate, wherein said first region is hermetically sealed by means of an insulator element electrostatically bonded to said planar periphery, comprising:

a planar insulator layer overlying said semiconductor substrate along the predetermined path of said feedthrough conductor across said periphery and having at least one planar projection extending out on each side of said path and shaped so as to come to a point;

a metal feedthrough conductor layer overlying said planar insulator layer having planar projections corresponding in position to said insulator layer projections such that said insulator layer is substantially covered by said feedthrough conductor layer except for a small border along the perimeter of said metal feedthrough conductor layer; and

said electrostatic bond formed at said planar periphery between said first and second regions creating a hermetic seal in the region of said feedthrough conductor layer by compression bonding of said insulator element to said projections of said insulator layer and said feedthrough conductor layer.

12. The apparatus of claim 11 wherein said feedthrough conductor layer comprises a layer of titanium deposited on the surface of said insulator layer and having a depth of approximately 0.1 microns.

13. The apparatus of claim 11 wherein said insulator layer comprises a layer of silicon dioxide subtractively etched on the surface of said semiconductor substrate and having a depth of approximately 0.1 microns.

14. The apparatus of claim 11 wherein said insulator element comprises a glass substrate.

15. The apparatus of claim 11 wherein each said planar projection of said planar insulator layer is formed along a path perpendicular to said predetermined path of said feedthrough conductor.

16. The apparatus of claim 11 wherein said planar insulator layer further overlies the outer edge of said planar periphery nearest said second region, said electrostatic bond formed at said planar periphery further creating a compression bond across the step formed by the planar insulator layer along said outer edge of said periphery;

and

said metal feedthrough conductor layer further defining a planar projection extending out on each side of the path of said feedthrough conductor layer shaped so as to come to a point substantially adjacent said edge of said insulator layer extending along the outer edge of said periphery.

17. The apparatus of claim 11 wherein said planar projections are positioned substantially in the middle of said periphery and wherein said planar insulator layer further includes a thin oxide line overlying said silicon and positioned in the middle of said periphery and extending from one of said planar projections formed in said planar insulator layer along said periphery until said oxide line contacts a next adjacent planar projection.

18. The apparatus of claim 11 further comprising means for coupling said feedthrough conductor to said semiconductor substrate during bonding;

and

means for eliminating said coupling once electrostatic bonding has been completed.

19. The apparatus of claim 18 wherein said means for coupling said feedthrough conductor to said semiconductor substrate comprises forming a conductive layer on the surface of said insulator element juxtaposed to said semiconductor substrate exterior to the region thereof electrostatically bonded to the silicon substrate and having a tab thereon formed to extend partly across the periphery so as to contact the feedthrough conductor when the insulator element is contiguous with the semiconductor substrate and means for coupling said metal layer to the silicon substrate, said means for eliminating said coupling comprising forming the metal layer in a part of the insulator element that is outside of the dicing line of the glass element such that when such dicing of the glass element occurs, the coupling between said tab and said silicon substrate is eliminated.

20. An apparatus for providing a hermetically sealed feedthrough conductor across the planar periphery between a first hermetically sealed region of a silicon substrate and a second region of said silicon substrate, wherein said first region is hermetically sealed by means of a glass substrate having a mesa surface on one surface thereof that is electrostatically bonded to said planar periphery, comprising:

a planar silicon dioxide layer overlying said silicon substrate along the predetermined path of said feedthrough conductor across said periphery and having at least one planar projection extending out on each side of said path so as to come to a sharp point and wherein said planar projections are positioned substantially in the middle of said periphery and wherein said planar insulator layer further includes a thin oxide line overlying said silicon substrate and positioned in the middle of said periphery and extending from one of said planar projections formed in said planar silicon dioxide layer along said periphery until said oxide line contacts a next adjacent planar projection; and

a metal feedthrough conductor layer overlying said silicon dioxide layer and having planar projections corresponding in position to said silicon dioxide layer projections such that said silicon dioxide layer is substantially covered by said feedthrough conductor layer except for a small border along the perimeter of said metal feedthrough conductor layer;

said electrostatic bond formed at said planar periphery between said first and second regions creating a hermetic seal in the region of said feedthrough conductor layer by compression bonding of said glass substrate to said projections of said silicon dioxide layer and said feedthrough conductor layer.

21. The apparatus of claim 20 wherein said hermetically sealed region of said silicon substrate includes an integrated circuit formed therein, said apparatus further comprising means for protecting said integrated circuit from damage during the electrostatic bonding of said glass substrate to said silicon substrate.