Pattern recognition system

• US 4,525,859 A
• Filed: 09/03/1982
• Issued: 06/25/1985
• Est. Priority Date: 09/03/1982
• Status: Expired due to Fees

• Current Assignee: Commonwealth Technology, Inc. (Kentucky) (Huntington Ingalls Industries Incorporated)
• Original Assignee: Commonwealth Technology, Inc. (Kentucky) (Huntington Ingalls Industries Incorporated)
• Inventors: Bowles, Romald E., Bowles, David E.
• Primary Examiner(s): Boudreau, Leo H.
• Assistant Examiner(s): NOT, DEFINED
• Application Number:
  US06/414,586
• Time in Patent Office: 1,026 Days
• Field of Search: 382/5, 382/27, 382/51, 382/52, 382/53, 382/54, 382/4, 356/71, 358/282
• US Class Current: 382/125
• CPC Class Codes: G06V 40/1347 Preprocessing; Feature extraction
• CPC Class Codes: G07C 9/37 using biometric data, e.g. fingerprints, iris scans or voice recognition

Abstract

A pattern recognition system which detects line bifurcations and line endings, denoted minutiae, in a pattern of lines such as are found in a fingerprint is disclosed. In one embodiment, an image of a pattern is focused on a conventional matrix of image sensors or pixels. An interface circuit serially reads the voltages from the pixels and applies them to an automatic, programmable threshold detector which optimally selects a cutoff voltage and outputs a binary signal representative of the presence of a point to a minutiae detection circuit. One part of this circuit electrically reforms the matrix on a first-in-first-out basis and simultaneously forms a smaller submatrix or window. Another part of the detection circuit determines firstly if a point is present in the central array of the window, and if so, secondly whether no more than two points, which are also contiguous, are present in the peripheral part of the submatrix. In such a case, a minutia has been located and a memory stores the address of the window.

Claims

1. A system for electronically investigating a pattern that can be divided into an array of points, the system comprising:

signal producing means for producing an electrical signal for each point on a matrix of points, said matrix having "K" points by "L" points, wherein K and L are real integers with one representing the points in the matrix line and the other representing the points in a matrix column, said signal producing means providing a serial stream of signals;

selecting means for progressively selecting locatable known groups of said produced electrical signals, which groups correspond to subarrays of said points, each said subarray having M lines by N columns, including a peripheral set of 2(M-2)+2N points and a central set of M×

N-2(M-2)-2N points, wherein said selecting means is comprised of a first storage means for storing and providing said electrical signals from said signal producing means on a first-in, first-out basis;

first determining means for checking and determining for each selected group of said signals whether a first, preselected number of signals corresponding to said central set of points have a first predetermined value and hence whether there is a central hit;

second determining means for checking and determining for each selected group of signals whether no more than a second, preselected number of the signals corresponding to said peripheral set of points have a second predetermined value, and hence whether there is a peripheral hit, wherein said second determining means comprises a memory means for storing 2²(M-2)+2N coded outputs, said memory means having an enable input and 2(M-2)+2N address lines which are connected to said 2(M-2)+2N peripheral storage cells; and

said first determining means comprises gate means, the inputs of which are connected to said central storage cells and the output of which is connected to said enable input, said gate means for providing an output signal to enable said memory means when said central storage cells contain said first preselected number of signals such that said memory means outputs the data stored at the memory address indicated by the signals stored in said peripheral storage cells;

third determining means responsive to said first and second determining means for determining the location of each subarray of points for which a central hit and a peripheral hit for the same group of corresponding signals were determined; and

memory means for storing each determined location.

2. The system as claimed in claim 1 and further comprising a clock means for generating system synchronization clock pulses;

and wherein

said signal producing means successively produces a plurality of signals, each signal representative of the density of the pattern at the corresponding point and produced in response to a clock pulse; and

said selecting means in response to a clock pulse selects a new group of signals.

3. The system as claimed in claim 1 wherein said first storage means is comprised of N-1 shift registers with each said shift register having L stages.

4. The system as claimed in claim 3 wherein said selecting means further is comprised of second storage means connected to said first storage means for selectively progressively storing and providing a predetermined number of signals and thus for forming a plurality of successive subarrays or window matrices.

5. The system as claimed in claim 4 wherein said first storage means is comprised of N-1 serially connected shift registers with each said shift register having "L" stages;

and wherein said second storage means is comprised of N serial-in, parallel-out (SIPO) shift registers, each said SIPO shift register having M stages and the input of each of N-1 of said SIPO shift registers of said second storage means being connected to the output of a corresponding shift register of said first storage means.

6. The system as claimed in claim 5 wherein N equals M equals 4 and thus said second storage means is comprised of 4, four stage shift registers and thus each said window matrix having 12 peripheral storage cells and 4 central storage cells.

7. The system as claimed in claim 5 wherein the input to one of said SIPO shift registers of said second storage means is connected to said signal producing means in parallel with the input to the first one of said serially connected shift registers of said first storage means.

8. A system as claimed in claim 1 wherein said signal producing means comprises a responsive means responsive to a point on said pattern for producing an output that varies with that response, a threshold detecting means connected between said responsive means and said selecting means for making positive and negative comparisons of said responsive means output with a variable threshold and for producing a binary output signal indicative of said positive and negative comparisons, and a threshold varying means for varying said threshold.

9. A system as claimed in claim 8 wherein said responsive means produces an analog output and threshold varying means comprises a self tracking density slice circuit.

10. A system as claimed in claim 9 wherein said self tracking density slice circuit comprises a brightness peak detector that receives said responsive means output and that produces a voltage output signal, a computer for supplying a variable offset voltage signal, and a subtractor circuit for subtracting the computer generated offset signal from the peak detector output signal and for producing an output related thereto;

and wherein said threshold detecting means comprises a voltage comparator for comparing said output of said subtractor circuit with the inverse of said responsive means output.

11. A system as claimed in claim 8 wherein said threshold varying means comprises a calculating means for combining the total number of said threshold detecting means positive comparisons with the number of times a predetermined array is established by said threshold detecting means negative comparisons, and for producing an output based on said combining.

12. A system as claimed in claim 11 wherein said calculating means comprises a positive counter for counting the number of said threshold detecting means positive comparisons, a negative counter for counting the number of times said predetermined array is established by said threshold detecting means negative comparisons, and a dividing and averaging means for dividing the count of said positive counter and the count of said negative counter and for averaging the results of a plurality of said divisions.

13. A system as claimed in claim 12 wherein said dividing and averaging means comprises an electronic dividing circuit and a variable gain averaging circuit.

14. A system as claimed in claim 12 wherein said dividing and averaging means comprises a programmed digital computer and a digital to analog converter.

15. A system as claimed in claim 12 wherein said calculating means comprises a first and second shift register, each having a number of stages equal to the number of points in a line in the array of points, the output of said first shift register being connected to the input of said second shift register, and comprises gate means the inputs of which are connected to a predetermined number of the initial stages of said first and second shift registers and the output of which is connected to said negative counter.

16. A system as claimed in claim 1 and further comprising a spot noise corrector means for determining the location of an incorrect value in said electrical signals produced by said signal producing means.

17. A system as claimed in claim 16 wherein said spot noise corrector means comprises a first plurality of serially connected shift registers each having a number of stages equal to the number of points in a line in the array of points, and a second plurality of serial-in parallel-out shift registers, the inputs to all but the first of which are connected to the output of a corresponding shift register in said first plurality, comprises a spot noise detector means the inputs to which are connected individual to the outputs of each stage of said shift registers in said second plurality, and comprises a correcting means for correcting an incorrect value.

18. A system as claimed in claim 17 wherein said correcting means comprises an EXCLUSIVE OR gate, the inputs to which are connected to the output of the last shift register in said first plurality and to the output of said spot noise detector.

19. A system as claimed in claim 17 wherein said first plurality is comprised of two shift registers and said second plurality is comprised of 3 three stage shift registers.

20. The system as claimed in claim 17 wherein the input to the first serial-in, parallel-out shift register of said second plurality of shift registers is connected to said signal producing means in parallel with the input to the first one of said first plurality of shift registers.

21. The system as claimed in claim 1 wherein said second determining means comprises a decoder means having an enable input connected to said first determining means and having data inputs, said decoder means for producing when enabled a signal representing the decoded data inputs.

22. The system as claimed in claim 21 wherein said decoder means comprises a read only memory.

23. The system as claimed in claim 21 wherein said decoder means comprises a logic array.

24. The system as claimed in claim 23 wherein said logic array is a programmable logic array.

25. A system for electronically investigating a finger print pattern which can be divided into an array of points and for identifying an individual based on the finger print of that individual, the system comprising signal producing means for producing electrical signals corresponding to said points, and which comprises a video camera means selecting means for progressively selecting locatable known groups of said produced electrical signals, which groups correspond to subarrays of said points, each said subarray having M lines by N columns, including a peripheral set of 2(M-2)+2N points and a central set of M×

N-2(M-2)-2N points;

first determining means for checking and determining for each selected group of said signals whether a first, preselected number of the signals corresponding to said central set of points have a first predetermined value and hence whether there is a central hit;

second determining means for checking and determining for each selected group of said signals whether no more than a second, preselected number of the signals corresponding to said peripheral set of points have a second predetermined value, and hence whether there is a peripheral hit;

third determining means responsive to said first and second determining means for determining the location of each subarray of points for which a central hit and a peripheral hit for the same group of corresponding signals were determined;

memory means for storing each determined location; and

an image enhancer for producing said pattern of lines from the finger print of an individual, said enhancer comprising a transparent window in optical communication with said video camera means, an elastomeric, light colored membrane and a viscous, opaque liquid interposed between said window and said membrane.

26. A system as claimed in claim 25 for identifying an individual based on the finger print of that individual, said system further comprising a finger determining means for determining the presence of a finger in engagement with said image enhancer.

27. An identification system as claimed in claim 26 wherein said finger determining means comprises a pressure transducer for detecting the pressure of said liquid, wherein a predetermined increase in liquid pressure signifies the presence of an object contacting said membrane.

28. An identification system as claimed in claim 27 wherein said finger determining means further comprises monitoring means for monitoring the changes in liquid pressure detected by said pressure transducer and comparing said changes with the expected changes resulting from a pulse in said finger, thereby indicating whether the object contacting said membrane is a human finger.

29. An identification system as claimed in claim 28 and further comprising means for determining whether the monitored pulse rate is normal for the individual being checked so to distinguish between an imposter.

30. An identification system as claimed in claim 26 wherein said finger determining means comprises a mechanical switch activated by a properly positioned finger.

31. An identification system as claimed in claim 26 wherein said finger determining means comprises a means for detecting the presence of heat emanating from said finger.

32. An identification system as claimed in claim 26 and further comprising computer means for receiving signals from said finger determining means and for activating said signal producing means, said selecting means and said first, second and third determining means upon the affirmative determination by said finger determining means of the presence of a finger.