High-density electronic processing package-structure and fabrication

• US 4,525,921 A
• Filed: 07/25/1983
• Issued: 07/02/1985
• Est. Priority Date: 07/13/1981
• Status: Expired due to Term

• Current Assignee: Irvine Sensors Corp.
• Original Assignee: Irvine Sensors Corp.
• Inventors: Clark, Stewart A., Carson, John C.
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Schiavelli, Alan E.
• Application Number:
  US06/517,221
• Time in Patent Office: 708 Days
• Field of Search: 29/572, 29/576 J, 29/577 C, 29/591, 357/75, 250/553, 250/578
• US Class Current: 438/109
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A high-density electronic package module is disclosed which comprises a stack of semiconductor chips having integrated circuitry on each chip. To permit the emplacement of thin film circuitry on the access ends, each access plane is etched to cut back the semiconductor material then covered with passivation material, and thereafter lapped to uncover the ends of electrical leads on the chips.

Claims

1. A method for fabricating a high-density electronic package having at least one access plane comprising:

providing a number of equal-sized semiconductor chips, each having integrated circuitry thereon, and each having a multiplicity of closely spaced electrical contact points at one end thereof;

stacking and bonding the semiconductor chips to form a rectangular parallelepiped structure with the electrical contact points in an array of closely spaced points on the access plane end of the stacked chips;

etching the access plane ends of the stacked chips to remove a small amount of the body material of the chips while leaving the contact points protruding;

depositing insulation material to cover the etched access plane ends of the stacked chips;

removing sufficient material from the insulation-covered ends of the stacked chips to uncover the electrical contact points; and

connecting a multiplicity of lead-out conductors to the insulation-covered ends of the stacked chips in such a way that each conductor is in electrical contact with one or more electrical contact points, while being otherwise insulated from the body material of the semiconductor chips.

2. A method for fabricating a high-density electronic package comprising:

providing a number of equal-sized semiconductor chips, each having integrated circuitry thereon, and each having a plurality of electrical contact points at one end thereof provided by the ends of the metal leads formed as part of the integrated circuitry on the substrate;

stacking and bonding the semiconductor chips to form a rectangular parallelepiped structure with the electrical contact points on an access plane end of the stacked chips;

etching the access plane end of the stacked chips to remove a small amount of the body material of the chips to leave the contact points protruding;

depositing insulation material on the etched ends of the stacked chips to cover the access plane;

removing sufficient material from the access plane to uncover the electrical contact points;

forming thin film conductors on the access plane to make contact with appropriate electrical contact points thereon, each conductor extending across the end of its contact points to provide a T-shaped junction; and

providing electrical connections leading from the conductors on the access plane to exterior circuitry.

3. The method of claim 2 wherein the step of etching the access plane end of the stacked chips is accomplished by a dry process using a gas plasma.

4. The method of claim 2 wherein the insulation material is a material which is applied in liquid form and then cured.

5. The method of claim 4 wherein the insulation material is a curable liquid polymer which is spun on and then cured.

6. The method of claim 5 wherein the insulation material is polyimide.

7. The method of claim 3 wherein the insulation material is a curable liquid polymer which is applied and then cured.