Data processing system

• US 4,527,237 A
• Filed: 04/14/1983
• Issued: 07/02/1985
• Est. Priority Date: 10/11/1979
• Status: Expired due to Fees

• Current Assignee: Cable Services Group, Inc. (CSG Systems International Incorporated)
• Original Assignee: Nanodata Computer Corporation
• Inventors: Wolff, Edward A., Kline, Mark H., Hughes, David T., Frieder, Gideon, Liebel, John T. Jr., Meier, David P.
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/483,444
• Time in Patent Office: 810 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 709/253
• CPC Class Codes: G06F 11/2736 using a dedicated service processor for test
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 15/161 Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning casings, cabinets, racks or drawers for data centers H05K5/00
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors

Abstract

A data processing system comprising an active and intelligent main store including a main memory, a main store controller for accessing the main memory in a manner allowing different address and data structures, and a main store bus connected to the controller. At least one processor of a first type is connected to the main store bus, this being an auxiliary processor for performing input-output and other operations. At least one processor of a second type also is connected to the main store bus, this being an execution processor for fetching, decoding and executing instructions. All or some of either or both of the auxiliary processors and execution processors may be different. A supervisory processor for initiating configuring and monitoring the system is connected to the main store bus. A communication bus is connected to the processors of the first and second types and to the supervisory processor. A diagnostic bus connects the supervisory processor to each of the processors of the first and second types. An input-output bus ensemble is connected to the supervisory processor and to each auxiliary processor. At least one device and associated device controller can be connected to the input-output bus ensemble. At least one direct memory access controller can be connected between the main store bus and the input-output bus ensemble.

Claims

1. A data processing system comprising:

(a) a plurality of execution processors, each functioning to fetch, decode and execute instructions;

(b) a plurality of auxiliary processors, each functioning to provide services not performed by said execution processors including systems support, input-output processing and special instruction support;

(c) a supervisory processor for initiating, configuring and monitoring said system;

(d) communication means common to all of said processors for connecting all of said processors in said system in a manner such that any processor can identify any other processor and thereby communicate with any other processor at high speed commensurate with the single instruction speed of any one processor in order to transfer control information and data associated with the control information through said system;

(e) said communication means being separate from the memory of said system and connecting said processors in a tightly coupled manner with all of said processors sharing a common memory space;

(f) said communication means connecting said processors in a manner such that said execution processors are capable of being different from one another and nonhomogeneous and said auxiliary processors are capable of being different from one another and nonhomogeneous; and

(g) whereby data, control, and diagnostic information can be transferred simultaneously through said system.

2. A data processing system according to claim 1, further including diagnostic bus means for connecting said supervisory processor to all of said processors in said system.

3. A data processing system according to claim 1, further including:

(a) main storage means; and

(b) main store bus means operatively connected to said main storage means and to said processors for enabling said processors to share said main storage means.

4. A data processing system according to claim 1, further including:

(a) an intelligent main store including main memory means and main memory control means operatively connected to said main memory means for accessing said main memory means in a manner allowing different address and data structures; and

(b) means for connecting said processors to said intelligent main store enabling said processors to share said memory.

5. A data processing system according to claim 1, further including:

(a) a bus arrangement comprising a plurality of additional buses;

(b) means for connecting said auxiliary processors in controlling relation to said bus arrangement; and

(c) said auxiliary processors comprising one category of processors and said execution processors comprising another category of processors;

(d) whereby each of said two categories of processors is capable of using the other of said two categories of processors as a pool.

6. A data processing system comprising:

(a) a plurality of processors;

(b) a communication bus for connecting all of said processors together;

(c) a bus arrangement comprising a plurality of additional buses;

(d) means for connecting any processor of a sub-set of said plurality of processors in controlling relation to said bus arrangement whereby any processor of said sub-set can control said bus arrangement, said sub-set dividing the plurality of processors into two groups of processors;

(e) each group of said processors being capable of using the other group of processors as a pool so that whatever function is performed by said other groups of processors can be assigned to a processor of said other group whose identity is not known to the assigning group of processors; and

(f) each individual processor of said plurality of processors being capable of communicating with each other individual processor through said communication bus, the message of said communication bus containing source identification bits and destination identification bits and each processor recognizing one or more of said identification bits, one of said bits being that processor'"'"'s own identification bit and the other of said bits being a pool identification.

7. A data processing system according to claim 6, wherein said processors of each of said two groups are capable of being different.

8. A data processing system according to claim 6, further including:

(a) a supervisory processor for initiating, configuring and monitoring said system;

(b) diagnostic bus means for connecting said supervisory processor to all of said processors in said system; and

(c) means for connecting said supervisory processor in controlling relation to said bus arrangement.

9. A data processing system comprising:

(a) a plurality of tightly coupled processors;

(b) main storage means separate from said processors;

(c) main store bus means operatively connected to main storage means and to said processors for enabling said processors to share said main storage means;

(d) communication bus means separate from said main store bus means for connecting all of said processors together in a tightly coupled manner with all of said processors sharing a common memory space and in a manner such that any processor can identify any other processor and thereby communicate with any other processor at high speed commensurate with the single instruction speed of any one processor in order to transfer control information and data associated with the control information through said system;

(e) a supervisory processor; and

(f) diagnostic bus means separate from said main store bus means and said communication bus means connected to and controlled by said supervisory processor for connecting said supervisory processor to all of said processors in said system for initiating, configuring and monitoring said system through said diagnostic bus means.

10. A data processing system according to claim 9, wherein said diagnostic bus means is operatively connected to said main storage means.

11. A data processing system according to claim 9, wherein said plurality of processors are arranged in at least two groups, said system further comprising:

(a) a bus arrangement comprising a plurality of additional buses; and

(b) means for connecting one of said two groups of processors in controlling relation to said bus arrangement.

12. A data processing system according to claim 11 further including means for connecting said supervisory processor in controlling relation to said bus arrangement.

13. A data processing system according to claim 12 further including means for connecting said supervisory processor to said communication bus means.

14. A data processing system comprising:

(a) main storage means;

(b) main storage bus means connected to said main storage means;

(c) a supervisory processor connected to said main storage bus means;

(d) at least one other processor, said other processor being connected to said main storage bus means, said other processor having its own storage means so that it does not use said main storage means as a programmed storage;

(e) communication bus means separate from said main store bus means connected to said supervisory processor and to said other processor;

(f) diagnostic bus means separate from said main store bus means and from said communication bus means connected in controlled relation to said supervisory processor for connecting said supervisory processor to said other processor in said system for initiating, configuring and monitoring said system through said diagnostic bus means; and

(g) an input-output bus ensemble connected to said supervisory processor and to said other processor, said other processor capable of being limited to providing transfer of information between said input-output bus ensemble and said main storage means;

(h) whereby said system has the capability of including additional ones of said other processors, said additional processors being of the same or of different types.

15. A data processing system comprising:

(a) an intelligent main store including main memory means, main memory control means connected to said main memory means for accessing said memory means and function means connected to said control means for providing memory management functions;

(b) main storage bus means connected to said main store;

(c) at least one execution processor connected to said main storage bus means for fetching, decoding and executing instructions;

(d) at least one auxiliary processor connected to said main storage bus means for providing services not performed by said execution processor including systems support, input-output processing and special instruction support;

(e) a supervisory processor connected to said main storage bus means;

(f) communication bus means connected to said auxiliary and execution processors and to said supervisory processor;

(g) diagnostic bus means connected in controlled relation to said supervisory processor for connecting said supervisory processor to each of said auxiliary and execution processors for initiating, configuring and monitoring said system through said diagnostic bus means;

(h) an input-output bus ensemble comprising an arrangement of a plurality of input-output buses connected to said supervisory processor and to said auxiliary processor, said auxiliary processor capable of being limited to providing transfer of information between said input-output bus ensemble and said main store means, and said execution processor capable of being limited to providing computational functions not involving information transfer from said input-output bus ensemble; and

(i) at least one direct memory access controller connected to said main storage bus means and to said input-output bus ensemble.

16. A data processing system according to claim 15, further including a plurality of said auxiliary processors, each being operatively connected to said main storage bus means, to said communication bus means, to said diagnostic bus means and to said input-output bus ensemble.

17. A data processing system according to claim 16, further including a corresponding plurality of said direct memory access controllers each operatively connected to said main storage bus means and to said input-output ensemble.

18. A data processing system according to claim 15, further including a plurality of said execution processors, each being operatively connected to said main storage bus means, to said communication bus means and to said diagnostic bus means.

19. A data processing system according to claim 18, wherein said execution processors are different from one another.