VCR backup system

• US 4,530,048 A
• Filed: 06/04/1982
• Issued: 07/16/1985
• Est. Priority Date: 06/04/1982
• Status: Expired due to Fees

• Current Assignee: Alpha Microsystems, Co.
• Original Assignee: Alpha Microsystems, Co.
• Inventors: Proper, John D.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Ungerman, Mark
• Application Number:
  US06/384,907
• Time in Patent Office: 1,138 Days
• Field of Search: 371/38, 371/10, 360/15, 360/32, 364/200 MS File, 364/900 MS File, 358/903, 340/347 DA
• US Class Current: 386/231
• CPC Class Codes: G06F 11/14 Error detection or correction of the data by redundancy in operation G06F11/16 takes precedence
• CPC Class Codes: G06F 3/06 Digital input from, or digital output to, record carriers , e.g. RAID, emulated record carriers or networked record carriers
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0682 Tape device
• CPC Class Codes: G11B 20/1879 Direct read-after-write methods
• CPC Class Codes: H04N 5/765 Interface circuits between an apparatus for recording and another apparatus

Abstract

The present invention is a video casette recorder (hereinafter referred to as "VCR") backup controller that can be installed in a S-100 bus system which is compatible with NTSC, PAL and SECAM systems. The controller provides temporary storage and control capability for the S100 interface bus system. The controller organizes the data into data blocks and synchronizes the data to TV signals during the write mode. The control further replicates data for error detection in the read and write modes.

Claims

1. A controller for coupling a video cassette recorder to a computer system bus, said bus adapted to transfer data on the bus to and from a computer, said controller comprising;

memory means for storing blocks of data, said blocks comprising a plurality of digital data bytes received from said bus for transfer to said video cassette recorder, and received from said video cassette recorder for transfer to said bus;

control means coupled to said bus and said memory means for generating control signals to cause digital data placed on said bus to be stored in said memory means, and to cause digital data stored in said memory means to be placed on said bus;

output means for transferring data from said memory means to said video cassette recorder; and

input means for transferring data from said video cassette recorder to said memory means;

wherein said output means comprises;

(i) horizontal sync and vertical sync and blanking means coupled to said control means for generating sync and blanking signals corresponding to a predetermined video format; and

(ii) digital to analog conversion means having said horizontal sync, vertical sync and blanking means, and said memory means connected as inputs for mixing said sync and blanking signals with data stored in said memory means to provide a mixed signal and converting the mixed signal to an output analog video signal; and

wherein said input means comprises;

(i) analog to digital conversion means for converting the data portions of an input analog video signal into a serial digital signal; and

(ii) parallelizer means having said analog to digital conversion means as an input and coupled to said memory means for converting said serial digital signal into digital data bytes prior to storing in said memory means.

2. The controller of claim 1 wherein said data on said bus means comprises parallel data, and further comprising serial means coupled to said control means for converting the parallel data on said bus into serial data prior to being inputted into the digital to analog conversion means.

3. The controller of claim 1 further comprising redundancy reducing code generation means coupled to said input means and said output means for generating redundancy codes for the data transferred between said bus and said video cassette recorder;

and

wherein said output means further comprises replication means for replicating the data transferred from said bus, and associated redundancy codes, to said video cassette recorder; and

wherein said input means further comprises error detection means coupled to said parallelizer means for detecting errors in the data portions of said analog video signal.

4. The controller of claim 3 wherein said error detection means comprises a sync byte detection means for detecting the first byte of a data block, and a zero detection means coupled to said analog to digital converter means for detecting an introductory signal preceding each data block.

5. The controller of claim 4 wherein said introductory signal comprises at least 32 logical "0"s.

6. The controller of claim 1 wherein said memory means comprises a random access memory for storing a plurality of data blocks and direct memory access means for buffering data transferred by said input means and said output means.

7. The controller of claim 1, wherein said mixed signal and said serial digital signal are comprised of data bytes, each data byte having a start bit, a stop bit, and data bits therebetween.

8. The controller of claim 7, further comprising means for generating said start bit and stop bit for each data byte.

9. The controller of claim 1, wherein said data is transferred by said input means and said output means in blocks comprised of at least 518 data bytes.

10. The controller of claim 1, further comprising first multiplexing means coupled to said control means for generating a first read data start bit in response to a read command for each and every data byte, and for generating a first write data start bit in response to a write command for each and every data byte.

11. The controller of claim 1, further comprising means for providing a signal to said memory means, causing said memory means to sequentially store the data bit streams and for providing a signal to said error detection means causing the error detection means to replicate data upon receipt of a command from said command means and upon receipt of the serial data byte streams.

12. A video cassette recorder backup system comprising:

bus means for providing and receiving parallel data byte streams;

controller means for coupling a video cassette recorder to said bus means, said controller means comprising;

command means generating a read command for reading the data bytes onto said bus means or a write command for writing the data bytes from said bus means;

circuit means interconnecting said command means and said bus means for transfer of data bytes between said command means and bus means;

processing means for processing data bytes received from said command means;

memory means coupled to said command means and to said processing means for storing a plurality of said data bytes in sequential order of receipt;

serial means coupled to said memory means for converting said parallel data byte streams into serial data byte streams;

sync and blanking means for generating video sync and blanking signals;

digital to analog converter means for combining said sync and blanking signals with said serial data byte streams from said serial means and converting the combined signal to an analog video signal;

replication means coupled to said digital to analog converter means for replicating said analog video signal in data blocks a predetermined number of times;

analog to digital converter means for converting an analog video signal to a digital serial data bytes stream;

parallelizer means for converting said serial data byte stream from said analog to digital converter means into a parallel data byte stream, with said parallelizer means coupled to said memory means;

stream detection means for detecting said data byte stream from said analog to digital converter means;

sync byte detection means for detecting the first data byte of each serial data byte stream received from said parallelizer means;

error detection means for detecting errors in said data bytes to determine whether an error is contained therein; and

means for ignoring subsequent replicated data blocks when no error is detected in a block of data bytes.

13. The controller of claim 12, further comprising first multiplexing means coupled to said command means for generating a read data start bit in response to a read command into said parallelizing means, and a write data start bit in response to a write command into said serial means.

14. The controller of claim 12 further comprising second multiplexing means for providing a signal to said memory means causing said memory means to sequentially store the data byte streams.

15. The controller of claim 12 further comprising means coupled to analog to digital means for generating a clock to clock each bit of each data byte into said parallelizer means.

16. A method for transferring data from a computer system bus to a video cassette recorder comprising the steps of:

placing parallel data bytes from the computer onto the bus;

isolating the bus from the video cassette recorder by temporarily storing one or more blocks of the parallel data bytes in predetermined locations in a random access memory;

converting stored blocks of parallel data bytes into a serial data stream;

converting the serial data stream into an analog video signal; and

writing the analog video signal to the video cassette recorder.

17. A method for transferring data from a video cassette recorder to a computer system bus comprising the steps of:

reading an analog video signal from said video cassette recorder;

removing the video sync and blanking signals from said analog video signal to provide a stripped video signal;

converting said stripped analog video signal into a serial data stream comprising one or more data blocks;

converting the serial data stream into a parallel bit stream comprised of parallel data bytes;

isolating the parallel data byte source from the bus by temporarily storing the parallel data bytes in a random access memory as one or more blocks of data; and

placing the stored parallel data bytes onto the bus without any video sync or blanking signals.

18. The method as defined in claim 17 including selecting desired data bytes from data blocks from the random access memory for placing onto the bus in response to a command request.

19. A controller for transferring data between a bus and a video line, with the data on the bus in parallel data byte streams without any video sync or blanking signals, said controller comprising in combination:

command means generating a read command for reading the data bytes onto the bus or a write command for writing the data bytes from the bus;

circuit means interconnecting said command means and the bus means for transfer of data bytes between said command means and the bus;

processing means for processing data bytes received from said command means;

memory means coupled to said command means and to said processing means for storing a plurality of said data bytes in sequential order of receipt;

serial means coupled to said memory means for converting said parallel data byte streams into serial data byte streams;

sync and blanking means for generating video sync and blanking signals;

digital to analog converter means for combining said sync and blanking signals with said serial data byte streams from said serial means and converting the combined signal to an analog video signal;

replication means coupled to said digital to analog converter means for replicating said analog video signal in data blocks a predetermined number of times;

connecting means for connecting said analog video signal to a video line;

analog to digital converter means for converting an analog video signal from a video line to a digital serial data byte stream;

parallelizer means for converting said serial data byte stream from said analog to digital converter means into a parallel data byte stream, with said parallelizer means coupled to said memory means;

stream detection means for detecting said data byte stream from said analog to digital converter means;

sync byte detection means for detecting the first data byte of each serial data byte stream received from said parallelizer means;

error detection means for detecting errors in said data bytes to determine whether an error is contained therein; and

means for ignoring subsequent replicated data blocks when no error is detected in a block of data bytes.

20. The controller of claim 19 further comprising first multiplexing means coupled to said command means for generating a read data start bit in response to a read command into said parallelizing means, and a write data start bit in response to a write command into said serial means.

21. The controller of claim 19 further comprising second multiplexing means for providing a signal to said memory means causing said memory means to sequentially store the data byte streams.

22. The controller of claim 19 further comprising means coupled to analog to digital means for generating a clock to clock each bit of each data byte into said parallelizer means.

23. A controller for coupling a video line to a bus, the bus being adapted to transfer data on the bus to and from a computer, said controller comprising in combination:

memory means for storing blocks of data, said blocks comprising a plurality of digital data bytes received from the bus for transfer to the video line, and received from the video line for transfer to the bus;

control means coupled to the bus and said memory means for generating control signals to cause digital data placed on the bus to be stored in said memory means, and to cause digital data stored in said memory means to be placed on the bus;

output means for transferring data from said memory means to the video line; and

input means for transferring data from the video line to said memory means;

wherein said output means comprises;

(i) horizontal sync and vertical sync and blanking means coupled to said control means for generating sync and blanking signals corresponding to a predetermined video format; and

(ii) digital to analog conversion means having said horizontal sync, vertical sync and blanking means, and said memory means connected as inputs for mixing said sync and blanking signals with data stored in said memory means to provide a mixed signal and converting the mixed signal to an output analog video signal; and

wherein said input means comprises;

(i) analog to digital conversion means for converting the data portions of an input analog video signal into a serial digital signal; and

(ii) parallelizer means having said analog to digital conversion means as an input and coupled to said memory means for converting said serial digital signal into digital data bytes prior to storing in said memory means.

24. The controller of claim 23 further comprising redundancy reducing code generation means coupled to said input means and said output means for generating redundancy codes for the data transferred between said bus and said video cassette recorder;

and

wherein said output means further comprises replication means for replicating the data transferred from said bus, and associated redundancy codes, to said video cassette recorder; and

wherein said input means further comprises error detection means coupled to said parallelizer means for detecting errors in the data portions of said analog video signal.

25. The controller of claim 23 wherein said memory means comprises a random access memory for storing a plurality of data blocks and direct memory access means for buffering data transferred by said input means and said output means.

26. The controller of claim 23 wherein said error detection means comprises a sync byte detection means for detecting the first byte of a data block, and a zero detection means coupled to said analog to digital converter means for detecting an introductory signal preceding each data block.

27. The controller of claim 26 wherein said introductory signal comprises at least 32 logical "0"s.

28. The controller of claim 23 wherein said mixed signal and said serial digital signal are comprised of data bytes, each data byte having a start bit, a stop byte, and data bits therebetween.

29. The controller of claim 28, further comprising means for generating said start bit for each data byte.

30. A method for transferring data from a bus to a video line, comprising the steps of:

placing parallel data bytes onto the data bus;

isolating the bus from the video line by temporarily storing one or more blocks of the parallel data bytes in a random access memory;

converting stored blocks of parallel data bytes into a serial data stream;

converting the serial data stream into an analog video signal; and

writing the analog video signal on the video line.

31. A method for transferring data from a video line to a bus, comprising the steps of:

reading an analog video signal from the video line;

removing the video sync and blanking signals from the analog video signal to provide a stripped video signal;

converting the stripped video signal into a serial data stream comprising one or more data blocks;

converting the serial data stream into a parallel bit stream comprised of parallel data bytes;

isolating the parallel data byte source from the bus by temporarily storing the parallel data bytes in a random accesss memory as one or more blocks of data; and

placing the stored parallel data bytes onto the bus without any video sync blanking signals.

32. The method as defined in claim 31 including selecting desired data bytes from the random access memory for placing onto the bus in response to a command request.