Pulse-width modulation circuit

• US 4,531,096 A
• Filed: 09/28/1983
• Issued: 07/23/1985
• Est. Priority Date: 10/09/1982
• Status: Expired due to Term

• Current Assignee: Nippon Yusen Kabushiki Kaisha
• Original Assignee: Nippon Yusen Kabushiki Kaisha
• Inventors: Yokoyama, Kenji
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US06/536,497
• Time in Patent Office: 664 Days
• Field of Search: 330/10, 330/207 A, 330/251, 332/9 R
• US Class Current: 330/10
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence

Abstract

A pulse-width modulation circuit of self-oscillation type produces a pulse-width modulated signal having a pulse width corresponding to an amplitude of an analog input signal. An integrator having an amplifier and at least one capacitor produces a triangle-wave signal. A comparator compares the triangle-wave signal with a reference voltage to generate a pulse signal. A delay circuit produces a delayed pulse signal in response to the pulse signal generated by the comparator. A feedback circuit feeds the delayed pulse signal back to an input terminal of the amplifier so that the self-oscillation is effected. The pulse-width modulated signal is derived from an output terminal of the delay circuit.

Claims

1. A pulse-width modulation circuit which comprises:

(a) amplifier means for amplifying an input signal inputted thereto to develop an amplified output signal from an output terminal thereof, said amplifier means having an inverting input terminal;

(b) capacitor means connected between the inverting input and output terminals of said amplifier means;

(c) comparator means for comparing the output signal of said amplifier means with a reference voltage to output a pulse signal, a pulse width of said pulse signal varying in accordance with a signal level of the output signal of said amplifier means;

(d) delay circuit means responsive to said pulse signal for producing an output pulse signal in delayed relation to said pulse signal for a certain period of time; and

(e) feedback circuit means for feeding the output pulse signal of said delay circuit means back to the inverting input terminal of said amplifier means;

(f) whereby a pulse-width modulated signal having a pulse width corresponding to an amplitude of said input signal appears at an output terminal of said delay circuit means.

9. A pulse-width modulation circuit according to any one of claims 1, 2, 3, 4, 5 and 7, in which said amplifier means further comprises a non-inverting input terminal and non-inversely amplifies said input signal applied to said non-inverting input terminal.

10. A pulse-width modulation circuit according to any one of claims 1, 2, 3, 4, 5 and 7, in which said amplifier means further comprises a non-inverting input terminal and inversely amplifies said input signal applied to said inverting input terminal, said non-inverting input terminal being grounded.

11. A pulse-width modulation circuit according to any one of claims 1, 2, 3, 4, 5 and 7, in which said amplifier means comprises an inverter composed of a CMOS gate.

12. A pulse-width modulation circuit according to any one of claims 1, 2, 3, 4, 5 and 7, in which said capacitor means comprises two capacitors serially connected between the inverting input and output terminals of said amplifier means, a junction point of said two capacitors being grounded through a resistor.

2. A pulse-width modulation circuit which comprises:

(a) amplifier means for amplifying an input signal inputted thereto to develop an amplified output signal from an output terminal thereof, said amplifier means having an inverting input terminal;

(b) capacitor means connected between the inverting input and output terminals of said amplifier means;

(c) comparator means for comparing the output signal of said amplifier means with a reference voltage to output a pulse signal, a pulse width of said pulse signal varying in accordance with a signal level of the output signal of said amplifier means;

(d) delay circuit means responsive to said pulse signal for producing an output pulse signal in delayed relation to said pulse signal for a certain period of time;

(e) pulse amplifier means for amplifying the output pulse signal of said delay circuit means; and

(f) feedback circuit means for feeding an output signal of said pulse means back to the inverting input terminal of said amplifier means;

(g) whereby a pulse-width modulated signal having a pulse width corresponding to an amplitude of said input signal appears at an output terminal of said pulse amplifier means.

3. A pulse-width modulation circuit comprising:

(a) amplifier means for amplifying an input signal inputted thereto to develop an amplified output signal from an output terminal thereof, said amplifier means having an inverting input terminal;

(b) capacitor means connected between the inverting input and output terminals of said amplifier means;

(c) inverter means comprised of a CMOS gate for converting the output signal of said amplifier means into a pulse signal, a pulse width of said pulse signal varying in accordance with a signal level of the output signal of the amplifier means;

(d) delay circuit means responsive to said pulse signal for producing an output pulse signal in delayed relation to said pulse signal for a certain period of time; and

(e) feedback circuit means for feeding the output pulse signal of said delay circuit means back to the inverting input terminal of said amplifier means;

(f) whereby a pulse-width modulated signal having a pulse width corresponding to an amplitude of said input signal appears at an output terminal of said delay circuit means.

4. A pulse-width modulation circuit comprising:

(a) amplifier means for amplifying an input signal inputted thereto to develop an amplified output signal from an output terminal thereof, said amplifier means having an inverting input terminal;

(b) capacitor means connected between the inverting input and output terminals of said amplifier means;

(c) inverter means comprised of a CMOS gate for converting the output signal of said amplifier means into a pulse signal, a pulse width of said pulse signal varying in accordance with a signal level of the output signal of the amplifier means;

(d) delay circuit means responsive to said pulse signal for producing an output pulse signal is delayed relation to said pulse signal for a certain period of time;

(e) pulse amplifier means for amplifying the output pulse signal of said delay circuit means; and

(f) feedback circuit means for feeding an output signal of said pulse amplifier means back to the inverting input terminal of said amplifier means;

(g) whereby a pulse-width modulated signal having a pulse width corresponding to an amplitude of said input signal appears at an output terminal of said pulse amplifier means.

5. A pulse-width modulation circuit comprising:

(a) amplifier means for amplifying an input signal inputted thereto to develop an amplified output signal from an output terminal thereof, said amplifier means having an inverting input terminal;

(b) capacitor means connected between the inverting input and output terminal of said amplifier means;

(c) comparator means for comparing the output signal of said amplifier means with a reference voltage to output a pulse signal, a pulse width of said pulse signal varying in accordance with a signal level of the output signal of the amplifier means;

(d) pulse amplifier means for amplifying the pulse signal outputted from said comparator means, said pulse amplifier means outputting an amplified pulse signal in a delayed relation to said pulse signal for a certain period of time; and

(e) feedback circuit means for feeding the output pulse signal of said pulse amplifier means back to the inverting input terminal of said amplifier means;

(f) whereby a pulse-width modulated signal having a pulse width corresponding to an amplitude of said input signal appears at an output terminal of said pulse amplifier means.

6. A pulse-width modulation circuit according to claim 5, in which said pulse amplifier means comprises a logical gate element.

7. A pulse-width modulation circuit comprising:

(a) amplifier means for amplifying an input signal inputted thereto to develop an amplified output signal from an output terminal thereof, said amplifier means having an inverting input terminal;

(b) capacitor means connected between the inverting input and output terminals of said amplifier means;

(c) inverter means comprised of a CMOS gate for converting the output signal of said amplifier means into a pulse signal, a pulse with of said pulse signal varying in accordance with a signal level of the output signal of the amplifier means;

(d) pulse amplifier means for amplifying the pulse signal outputted from said inverter means, said pulse amplifier means outputting an amplified pulse signal in a delayed relation to said pulse signal for a certain period of time; and

(e) feedback circuit means for feeding the output pulse signal of said pulse amplifier means back to the inverting input terminal of said amplifier means;

(f) whereby a pulse-width modulated signal having a pulse width corresponding to an amplitude of said input signal appears at an output terminal of said pulse amplifier means.

8. A pulse-width modulation circuit according to claim 7, in which said pulse amplifier means comprises output-stage switching elements, and an on-off timing control circuit for deactivating said output-stage switching elements for a certain period of time.