Capacitor array

• US 4,531,113 A
• Filed: 06/27/1983
• Issued: 07/23/1985
• Est. Priority Date: 06/27/1983
• Status: Expired due to Fees

• Current Assignee: GTE Laboratories Incorporated (Lumen Technologies, Inc.)
• Original Assignee: GTE Laboratories Incorporated (Lumen Technologies, Inc.)
• Inventors: Abraham, Leonard G.
• Primary Examiner(s): NOT, DEFINED
• Application Number:
  US06/508,363
• Time in Patent Office: 757 Days
• Field of Search: 340/347 AD, 340/347 C
• US Class Current: 341/136
• CPC Class Codes: H03M 1/74 Simultaneous conversion

Abstract

A capacitor array for a companded pulse code modulation voice codec includes a first plurality of capacitors having a common capacitance C each. A plurality of switching means individually and selectively couple one plate of each of the capacitors to a first point of reference potential or to a second point of reference potential. A second plurality of capacitors has a common capacitance 2C, each, which is coupled in series to form a plurality of junctions, each of the junctions being coupled to a separate one of second plates of the first plurality of capacitors.

Claims

1. A capacitor array for a companded pulse-code modulation voice codec comprising

a first plurality m of capacitors having a common capacitance C, each, and each of said capacitors having a first plate and a second plate;

a plurality of switching means for individually and selectively coupling said first plates of said capacitors to either a first point of reference potential or to a second point of reference potential; and

a second plurality n of capacitors having a common capacitance 2C, each, coupled in series to form a plurality (n+1) of junctions, each of said junctions being coupled to a separate one of said second plates,

a plurality of MOS transistors, each having a drain electrode, a source electrode, and a gate electrode;

means for coupling said drain electrodes, respectively, to said junctions;

means for coupling said source electrodes to said first point of reference potential; and

means for coupling said gate electrodes to an enabling signal,

wherein m and n are integers, and wherein the value of 2C is twice the value of C.

2. A capacitor array for a companded pulse-code modulation voice codec comprising

a first plurality m of capacitors having a common capacitance C, each, and each of said capacitors having a first plate and a second plate;

a plurality of switching means for individually and selectively coupling said first plates of said capacitors to a first point of reference potential of a given polarity or to a second point of reference potential;

a first capacitor having a like capacitance C having a first plate adapted to be coupled to said second point of reference potential and having a second plate;

a second capacitor having a like capacitance C having a first plate adapted to be coupled to a third point of reference potential equal in magnitude but opposite in polarity to that of said first point of reference potential, and having a second plate;

a third capacitor having a like capacitance C having a first plate and a second plate;

a first switch having an arm coupled to said first plate of said third capacitor, said arm being adapted to be coupled to either a first terminal or a second terminal;

means for coupling said second plates of said first capacitor and said second capacitor together at a first coupling point;

means for coupling said second plate of one of said first plurality of capacitors and said second plate of said third capacitor together at a second coupling point;

a second plurality m of capacitors having a common capacitance 2C, each coupled in series to form a plurality (m+1) of junctions, each of said junctions being coupled to a respective one of said second plates of said first plurality of capacitors and said second capacitor;

a second switch having an arm coupled to said second coupling point and being adapted to be coupled to said second point of reference potential,

said first switch and said second switch being so ordered that

(a) when said arm of said first switch is coupled to said first terminal, said arm of said second switch is open circuited, and

(b) when said arm of said first switch is coupled to said second terminal, said arm of said second switch is coupled to said second point of reference potential; and

means for coupling said first terminal to said second point of reference potential,

said second terminal being adapted to receive an input signal.

3. The capacitor array as recited in claim 2 further comprising means for preventing a charge buildup on junctions of said second plurality of capacitors.

4. The capacitor array as recited in claim 2 further comprising

a plurality of MOS transistors, each having a drain electrode, a source electrode, and a gate electrode;

means for coupling said drain electrodes, respectively, to said junctions;

means for coupling said source electrodes to said second point of reference potential; and

means for coupling said gate electrodes to an enabling signal.

5. The array as recited in claim 6 wherein m=12.

6. The array as recited in claim 2 wherein distributive stray capacitance can be present between said second coupling point and said second point of reference potential without material effect.

7. A capacitor array for a companded pulse-code modulation voice codec comprising

m capacitors, where m≧

5, having a common capacitance C, each, and each of said capacitors having a first plate and a second plate;

switching means for individually and selectively coupling said first plate of the first, second, third, fourth, excluding the fifth, and thereafter up to the m^th capacitors of said m capacitors to a first point of reference potential of a given polarity and to a second point of reference potential, and for selectively coupling said first plate of the fifth of said m capacitors to said second point of reference potential and to a third point of reference potential equal in magnitude but opposite in polarity to that of said first point of reference potential;

a first additional capacitor having a like capacitance C having a first plate adapted to be coupled to said second point of reference potential and having a second plate;

a second additional capacitor having a like capacitor C having a first plate adapted to be coupled to said third point of reference potential, and having a second plate;

a third additional capacitor having a like capacitance C having a first plate and a second plate;

a first switch having an arm coupled to said first plate of said third additional capacitor, said arm being adapted to be coupled to either a first terminal or a second terminal;

means for coupling said second plates of said first additional capacitor and said second additional capacitor together at a first coupling point;

P1 means for coupling said second plate of one of said m capacitors and said second plate of said third additional capacitor together at a second coupling point;

m capacitors having a common capacitance 2C, each, each coupled in series to form (m+1) junctions, each of said junctions being coupled to a respective one of said second plates of said m capacitors having said common capacitance C each, and said second plate of said second capacitor;

a second switch having an arm coupled to said second coupling point and being adapted to be coupled to said second point of reference potential,

said first switch and said second switch being so ordered that

(a) when said arm of said first switch is coupled to said first terminal, said arm of said second switch is open circuited, and

(b) when said arm of said first switch is coupled to said second terminal, said arm of said second switch is coupled to said second point of reference potential; and

means for coupling said first terminal to said second point of reference potential,

said second terminal being adapted to receive an input signal.

8. The capacitor array as recited in claim 7 further comprising means for preventing a charge buildup on junctions of said second plurality of capacitors.

9. The capacitor array as recited in claim 7 further comprising

a plurality of MOS transistors, each having a drain electrode, a source electrode, and a gate electrode;

means for coupling said drain electrodes, respectively, to said junctions;

means for coupling said source electrodes to said second point of reference potential; and

means for coupling said gate electrodes to an enabling signal.

10. The array as recited in claim 7 wherein m=12.

11. The array as recited in claim 7 wherein distributive stray capacitance can be present between said second coupling point and said second point of reference potential without material effect.

12. A capacitor array for a companded pulse-code modulation voice codec comprising

a first plurality of eight capacitors having a common capacitance C, each, and each of said capacitors having a first plate and a second plate;

means for coupling all of said first plates of said eight capacitors together to a first point of reference potential;

a second plurality of eight capacitors having a common capacitance 2C, each coupled in series to form nine junctions;

switching means for individually and selectively coupling eight contiguous of said nine junctions to said second plates of said first plurality of eight capacitors, or to a first common line;

a first additional capacitor having a like capacitor C having a first plate and a second plate;

a first switch having an arm coupled to said first plate of said first additional capacitor, said arm being adapted to be coupled to either a first terminal or a second terminal;

a second switch having an arm coupled to said second plate of the eighth capacitor of said first plurality of capacitors and being adapted to be coupled to said first plates of said first plurality of capacitors;

said first switch and said second switch being so ordered that

(a) when said arm of said first switch is coupled to said first terminal, said arm of said second switch is open circuited, and

(b) when said arm of said second switch is coupled to said second terminal, said arm of said second switch is coupled to said first plates of said first plurality of capacitors;

means for coupling said second plate of said first additional capacitor to said second plate of said eighth capacitor of said first plurality of capacitors;

means for coupling said first terminal to said first plates of said first plurality of capacitors, said second terminal being adapted to receive an input signal;

a step subcircuit comprising

a third plurality of four capacitors having a common capacitance C, each, and each having a first plate and a second plate,

a like third plurality of four switches, each having an arm coupled to a respective first plate of said third plurality of four capacitors, adapted to switch between respective terminals for receiving a reference voltage of a given polarity, and to a first point of reference potential,

a second additional capacitor having a capacitance C coupled across a first of said third plurality of four capacitors and said first point of reference potential,

a third additional capacitor having a capacitance C having a first plate and a second plate,

means for coupling said first plate of said third additional capacitor to said reference voltage of a given polarity, and

a fourth plurality of five capacitors having a common capacitance 2C, each, each coupled in series to form six junctions, one junction of which is coupled to said second plate of said first capacitor of said third plurality of four capacitors, a second junction of which is coupled to said second plate of a second capacitor of said third plurality of four capacitors, a third junction of which is coupled to said second plate of a third capacitor of said third plurality of four capacitors, a fourth junction of which is coupled to said second plate of a fourth capacitor of said third plurality of four capacitors, a fifth junction of which is coupled to said second plate of said third additional capacitor, and a sixth junction of which is coupled to said first common line; and

a bias subcircuit comprising

a fifth plurality of five capacitors having a common capacitance C, each, and each having a first plate and a second plate, a fourth additional capacitor having a capacitance C and having a first plate and a second plate, a fifth additional capacitor having a capacitance C and having a first plate and a second plate,

means coupling said first plates of said fifth plurality of five capacitors to a first point of reference potential,

means for coupling said first plates of said fourth additional capacitor and said fifth additional capacitor to a reference voltage that is equal in magnitude but opposite in polarity to said reference voltage of a given polarity,

a sixth plurality of five capacitors having a capacitance of 2C, each, coupled in series to form six junctions, one junction of which is coupled to both said second plate of said fourth additional capacitor and to the remaining ninth junction of said second plurality of eight capacitors, a second junction of which is coupled to said second plate of a first capacitor of said fifth plurality of five capacitors, a third junction of which is coupled to said second plate of a second capacitor of said fifth plurality of five capacitors, a fourth junction of which is coupled to said second plate of a third capacitor of said fifth plurality of five capacitors, a fifth junction of which is coupled to said second plate of a fourth capacitor of said fifth plurality of five capacitors, and a sixth junction of which is coupled to both said second plate of a fifth capacitor of said fifth plurality of five capacitors and to said second plate of said fifth additional capacitor.