Video device synchronization system

• US 4,532,547 A
• Filed: 03/31/1982
• Issued: 07/30/1985
• Est. Priority Date: 03/31/1982
• Status: Expired due to Term

• Current Assignee: Ampex Corporation (Delta Information Systems, Inc.)
• Original Assignee: Ampex Corporation (Delta Information Systems, Inc.)
• Inventors: Bennett, Phillip P.
• Primary Examiner(s): Martin, John C.
• Assistant Examiner(s): Peng, John K.
• Application Number:
  US06/363,670
• Time in Patent Office: 1,217 Days
• Field of Search: 358/17, 358/18, 358/19, 358/20, 358/148, 358/149, 358/181, 358/324, 358/325, 358/326, 358/337, 358/338, 358/339
• US Class Current: 348/518
• CPC Class Codes: C10M 2205/00 Organic macromolecular hydrocarbon compounds or fractions, whether or not modified by oxidation as ingredients in lubricant compositions
• CPC Class Codes: C10M 2205/06 containing conjugated dienes
• CPC Class Codes: C10M 2207/027 Neutral salts thereof
• CPC Class Codes: C10M 2207/028 Overbased salts thereof
• CPC Class Codes: C10M 2207/123 polycarboxylic
• CPC Class Codes: C10M 2207/125 having hydrocarbon chains of eight up to twenty-nine carbon atoms, i.e. fatty acids
• CPC Class Codes: C10M 2207/129 having hydrocarbon chains of thirty or more carbon atoms
• CPC Class Codes: C10M 2207/144 containing hydroxy groups
• CPC Class Codes: C10M 2207/146 having carboxyl groups bound to carbon atoms of six-membeered aromatic rings having a hydrocarbon substituent of thirty or more carbon atoms
• CPC Class Codes: C10M 2207/16 Naphthenic acids
• CPC Class Codes: C10M 2207/18 Tall oil acids
• CPC Class Codes: C10M 2207/20 Rosin acids
• CPC Class Codes: C10M 2207/22 Acids obtained from polymerised unsaturated acids
• CPC Class Codes: C10M 2207/262 derived from hydroxy substituted aromatic acids, e.g. salicylates
• CPC Class Codes: C10M 2207/282 of (cyclo)aliphatic oolycarboxylic acids
• CPC Class Codes: C10M 2207/287 Partial esters
• CPC Class Codes: C10M 2207/288 containing free carboxyl groups
• CPC Class Codes: C10M 2207/289 containing free hydroxy groups
• CPC Class Codes: C10M 2207/34 Esters having a hydrocarbon substituent of thirty or more carbon atoms, e.g. substituted succinic acid derivatives
• CPC Class Codes: C10M 2215/04 having amino groups bound to acyclic or cycloaliphatic carbon atoms
• CPC Class Codes: C10M 2215/042 : containing hydroxy groups; Alkoxylated derivatives thereof
• CPC Class Codes: C10M 2215/08 : Amides
• CPC Class Codes: C10M 2215/082 : containing hydroxyl groups; Alkoxylated derivatives
• CPC Class Codes: C10M 2215/086 : Imides
• CPC Class Codes: C10M 2215/26 : Amines
• CPC Class Codes: C10M 2215/28 : Amides; Imides
• CPC Class Codes: C10M 2217/046 : Polyamines, i.e. macromoleculars obtained by condensation of more than eleven amine monomers
• CPC Class Codes: C10M 2217/06 : Macromolecular compounds obtained by functionalisation op polymers with a nitrogen containing compound
• CPC Class Codes: C10M 2219/02 : Sulfur-containing compounds obtained by sulfurisation with sulfur or sulfur-containing compounds
• CPC Class Codes: C10M 2219/022 : of hydrocarbons, e.g. olefines polyolefins C10M2221/041
• CPC Class Codes: C10M 2219/024 : of esters, e.g. fats
• CPC Class Codes: C10M 2219/044 : Sulfonic acids, Derivatives thereof, e.g. neutral salts
• CPC Class Codes: C10M 2219/046 : Overbasedsulfonic acid salts
• CPC Class Codes: C10M 2219/082 : containing sulfur atoms bound to acyclic or cycloaliphatic carbon atoms
• CPC Class Codes: C10M 2219/087 : containing hydroxy groups; Derivatives thereof, e.g. sulfurised phenols
• CPC Class Codes: C10M 2219/088 : Neutral salts
• CPC Class Codes: C10M 2219/089 : Overbased salts
• CPC Class Codes: C10M 2223/04 : Phosphate esters
• CPC Class Codes: C10M 2223/042 : Metal salts thereof
• CPC Class Codes: C10M 2223/045 : Metal containing thio derivatives
• CPC Class Codes: C10N 2010/00 : Metal present as such or in compounds
• CPC Class Codes: C10N 2010/02 : Groups 1 or 11
• CPC Class Codes: C10N 2010/04 : Groups 2 or 12
• CPC Class Codes: C10N 2010/06 : Groups 3 or 13
• CPC Class Codes: C10N 2010/08 : Groups 4 or 14
• CPC Class Codes: C10N 2010/10 : Groups 5 or 15
• CPC Class Codes: C10N 2010/12 : Groups 6 or 16
• CPC Class Codes: C10N 2010/14 : Group 7
• CPC Class Codes: C10N 2040/25 : Internal-combustion engines
• CPC Class Codes: C10N 2040/251 : Alcohol fueled engines
• CPC Class Codes: C10N 2040/255 : Gasoline engines
• CPC Class Codes: C10N 2040/28 : Rotary engines
• CPC Class Codes: H04N 5/0736 : using digital storage buffer techniques

Abstract

A TV video signal synchronization signal system enables a video device such as a digital special effects system to operate synchronously in response to an input video signal and still produce an output video signal synchronized to a television studio locking reference signal. The video device and the synchronization signal generating subsystem thereof operate in response to a pixel rate clock of approximately 70 ns and in response to a phase command to generate timing for the horizontal sync pulse, color burst signal and video data of the output video signal. The output color burst signal remains phase locked to the locking reference signal with output gating being responsive to the phase command. A ROM interpolator provides subpixel accuracy for the output horizontal sync pulse while output line buffering and interpolation permits the output video data to be phase matched to the reference master sync signal. The entire video system thus operates synchronously with the input video signal to avoid noise interference problems which result from multiple phase clock signals while generating a composite output video signal that is properly phase synchronized with a studio locking reference signal.

Claims

1. A video device synchronization system comprising:

a phase detector coupled to receive a first video device synchronization signal and a locking reference signal and generate a phase difference signal indicative of any phase difference therebetween; and

a signal generator coupled to receive a second video device synchronization signal and a phase difference command signal that is responsive to the phase difference signal and generate, as an output, a video synchronization signal having a phase difference relative to the second video device synchronization signal received by the signal generator indicated by the phase difference command signal.

2. The video synchronization system according to claim 1 above, further comprising a transducer coupled to generate an operator selected offset phase adjustment signal and an adder coupled to receive the phase difference signal and the offset phase adjustment signal and to generate the phase difference command signal as a sum thereof.

3. The video synchronization system according to claim 1 or 2 above, further comprising a sinewave generator coupled to generate a color burst signal phase locked to a color burst signal component of the locking reference signal, the sinewave generator further including an output gate coupled to enable the output of the generated color burst signal during a time interval defined by at least one gating signal received from the signal generator, the synchronization system further including a phase adjust circuit coupled to selectively adjust the phase of the generated color burst signal by an operator selected magnitude and the signal generator further including means responsive to the second video device synchronization signal received thereby and the phase difference command signal for generating the at least one gating signal.

4. The video synchronization system according to claim 1 above, wherein the phase detector includes a counter coupled to count clock pulses during an interval of time corresponding to a phase difference between the first video device synchronization signal and the locking reference signal.

5. The video synchronization system according to claim 4 above, wherein the first video device synchronization signal received by the phase detector is a horizontal sync signal and the phase difference signal represents a count accumulated over a plurality of occurrences thereof.

6. The video synchronization system according to claim 5 above, wherein the clock signal is provided with four equally spaced phases and including a multiplexer coupled to sequentially provide successive phases of the clock signal to the counter during successive occurrences of a phase difference between the first video device synchronization signal received by the phase detector and the locking reference signal.

7. A video device synchronization system for a video device coupled to receive and operate in response to an input video signal, the synchronization system comprising:

a phase detector coupled to receive signals indicating phase relationships of the input video signal and a master sync signal and to generate a phase count signal indicative of the phase difference therebetween;

a transducer coupled to generate a phase adjustment signal indicative of an operator selected phase adjustment;

an adder coupled to add the operator selected phase adjustment to the phase difference indicated by the phase count signal to produce a phase command signal indicative of a commended phase difference relative to the input video signal; and

a synchronizing signal generator coupled to receive a pixel rate clock signal synchronized to the input video signal, a signal indicative of the phase of the input video signal and the phase command signal and to generate under control of the pixel rate clock signal at least one output timing signal having a phase relationship to the phase of the input video signal determined in response to the phase command signal.

8. The synchronization system according to claim 7 above, wherein the at least one output timing signal includes a horizontal synchronization pulse for each horizontal line of a video image.

9. A video device synchronization system comprising:

an input sync detector and clock generator coupled to receive a composite video input signal and generate timing and control signals synchronized therewith, the timing and control signals including a pixel clock signal, a master frame reset signal and an input horizontal sync signal having the same phase as the horizontal sync pulses of the composite video input signal;

a phase detector coupled to receive the input horizontal sync signal and a reference locking signal and generate a phase count signal indicative of any phase difference therebetween; and

a synchronization signal generator coupled to receive the master frame reset signal and information indicative of the phase count signal and to generate a composite sync signal having a phase relative to the master frame reset signal determined by the information indicative of the phase count signal.

10. A video device synchronization system comprising:

an input sync detector and clock generator coupled to receive a composite video input signal and generate timing and control signals synchronized therewith, the timing and control signals including a pixel clock signal, a master frame reset signal and an input horizontal sync signal having the same phase as the horizontal sync pulses of the composite video input signal;

a phase detector coupled to receive the input horizontal sync signal and a reference locking signal and generate a phase count signal indicative of any phase difference therebetween;

a synchronization signal generator coupled to receive the master frame reset signal and information indicative of the phase count signal and to generate a composite sync signal and an output horizontal burst gate signal having a phase relative to the master frame reset signal determined by the information indicative of the phase count signal; and

a color burst generator including a phase locked loop generating an output color subcarrier signal that is phase locked to a color subcarrier component of the reference locking signal and an output gating circuit coupled to selectively gate therethrough the output color subcarrier signal in response to the output horizontal burst gate signal to produce a gated output color subcarrier signal.

11. The video device synchronization system according to claim 10 above, further comprising an operator controllable phase adjust circuit coupled to receive the gated output color subcarrier signal and adjust the phase thereof by an operator selected amount.

12. The video device synchronization system according to claim 9 or 10 above, wherein the information indicative of the phase count signal is a phase difference command signal and the synchronization signal generator includes a pixel counter controlling the phase relationship of signals generated by the synchronization signal generator, the pixel counter being coupled to be loaded with the phase difference command signal upon each occurrence of the master frame reset signal.

13. The video device synchronization system according to claim 9 or 10 above, further comprising a transducer generating an offset phase adjustment signal indicating a desired phase adjustment in response to an operator command and an adder coupled to generate the information indicative of the phase count signal as a sum of the offset phase adjustment signal and the phase count signal.

14. A video device comprising:

a video signal combiner coupled to receive output video data, an output composite sync signal and an output color burst signal and generate as an output a composite video output signal in response thereto;

an input sync detector and clock generator circuit coupled to receive a composite video input signal and generate timing and control signals synchronized therewith, the timing and control signals including a pixel rate clock signal, a master frame reset signal and, an input horizontal sync signal;

a phase detector coupled to receive the input horizontal sync signal and a reference master sync signal component of a locking reference signal and generate a phase count signal indicative of any phase difference therebetween;

a video transformation device coupled to receive the composite video input signal, the master frame reset signal, and the pixel rate clock signal, and to generate as outputs status information and transformed video data having a phase delayed by an integral number of frame times relative to video data of the composite video input signal;

an output buffer and interpolator coupled to receive transformed video data from the video transformation device, receive a phase difference command signal responsive to the phase count signal, store the transformed video data and provide the transformed video data to the video signal combiner with a phase relationship relative to the composite video input signal that is responsive to the phase difference command signal;

a synchronization signal generator coupled to receive the master frame reset signal and the phase difference command signal and to generate said output composite sync signal and an output horizontal burst gate signal with a phase relative to the master frame reset signal determined by the ph signal and an output horizontal burst gate signal with a phase relative to the master frame reset signal determined by the phase difference command signal;

a processor coupled to receive timing and control signals from the input sync detector and clock generator circuit and operate in response thereto to receive said status information from the video transformation device and generate said control information in response thereto, and to receive said phase count signal and generate said phase difference command signal in response thereto; and

a color burst generator coupled to receive a reference color burst signal component of the locking reference signal and the output horizontal burst gate signal, the color burst generator being coupled to generate a color subcarrier sinewave signal phase locked to the reference color burst signal and to gate the subcarrier sinewave signal under control of the output horizontal burst gate signal to generate said output color burst signal.

15. A video device synchronization system for synchronizing an output video sync signal relative to a reference timing signal in response to periodically occurring input video sync signals, comprising

a phase detector responsive to an input video sync signal and the reference timing signal to generate a phase difference signal indicative of the phase difference therebetween;

and

a signal generator responsive to a selected input video sync signal and the phase difference signal to generate an output video sync signal having a phase relative to the selected input video sync signal determined by the phase difference signal.

16. A video device synchronization system according to claim 15 wherein said input video sync signals are horizontal sync signals.

17. A video device synchronization according to claim 16 wherein said selected input video signal is a said horizontal sync signal corresponding to a master frame reset signal generated once per frame.

18. A video device synchronization system according to any one of claims 15 to 17 wherein the phase detector is responsive to a multiplicity of occurrences of respective input video sync and reference timing signals and generates a phase difference signal corresponding to the sum of the phase differences between respective pairs of the multiplicity of input video sync signals and reference timing signals.