System for periodically reading all memory locations to detect errors

• US 4,532,628 A
• Filed: 02/28/1983
• Issued: 07/30/1985
• Est. Priority Date: 02/28/1983
• Status: Expired due to Fees

• Current Assignee: The Perkin-Elmer Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: The Perkin-Elmer Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Matthews, David J.
• Primary Examiner(s): Smith, Jerry
• Assistant Examiner(s): Ungerman, Mark
• Application Number:
  US06/470,901
• Time in Patent Office: 883 Days
• Field of Search: 371/13, 371/21, 371/38, 365/200, 365/201, 364/200 MS File, 364/900 MS File
• US Class Current: 714/6.2
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/2289 by configuration test
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/18 Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
• CPC Class Codes: G11C 29/88 with partially good memories

Abstract

A memory checking circuit for periodically reading the data from all locations therein. The circuit includes logic to correct and restore data from locations where an error has occurred. The circuit quickly identifies all memory locations present during search mode at a fast rate and reads all present locations at a slower rate during normal mode.

Claims

1. In a computer system including a solid state memory with a plurality of addressable locations and an error detector/corrector circuit for checking data as it is read from the memory and correcting the data if a detectable error has occurred, the corrected data being stored in the addressed memory location to assure that the correct data is in memory, a circuit to identify all directly addressable memory locations present and to periodically read each present location comprising, in combination:

address generator means operative during a search mode for producing each directly addressable memory location;

read request means to request, during said search mode, that each address produced by said address generator be read by the memory;

storage means responsive to each read request to store an indication from the memory whether the addressed location is present or not present;

said address generator operative during a normal run mode to generate periodically all possible directly addressable locations at a rate slower than addresses are generated thereby during said search mode;

means operative during normal run mode, and responsive to said storage means and said address generator to initiate a memory read whenever the address produced by said address generator is indicated to be present by the data in said storage means.

2. In a digital computer system including a memory with a plurality of individually addressable locations, each location for storing data for later retrieval, and a data error detect and a correct circuit for checking the data as it is read from a memory location and correcting the data if a correctable error has occurred, a circuit to identify all present memory locations during a search mode and to periodically read all present memory locations during normal run mode and to correct the data at each present location where a data error is detected on reading the data from the addressable location comprising, in combination:

mode defining means alternatively defining a search mode or a normal mode;

address generator means responsive to said mode defining means being in said search mode to generate in succession each possible memory address and to apply the produced address to the memory, the memory producing an indication whether the addressed location is present or not present;

storage means responsive to said mode defining means being in said search mode to store for each possible memory address, said indication from the memory indicating whether the addressed location is present or not;

said mode defining means being responsive to said address generator means having once produced each possible memory address for which said storage means has stored an indication whether the location is present or not to change the mode to said normal mode;

said address generator being responsive to said mode defining means being in said normal mode to periodically generate all possible memory addresses at a rate slower than the rate of address generation during said search mode, said address generator being operative to apply said memory address to said memory if said indication in said storage means for said generated address indicates the corresponding memory location is present.

3. A method for refreshing a solid state memory with a plurality of addressable locations, the method comprising the steps of:

attempting to address during a search mode all possible memory address locations;

storing during said search mode an indication whether each address location is present in the system;

periodically generating during a normal mode all possible memory addresses at a rate slower than the addresses were produced during said search mode; and

reading and restoring each periodically generated memory address location during said normal mode when the address thereof is generated and when the indication for that address location is that it is present in the system, the restored data being corrected as needed in accordance with an error correction code stored with each addressed location.