Circuit arrangement for identifying and storing power line faults

• US 4,533,865 A
• Filed: 02/09/1983
• Issued: 08/06/1985
• Est. Priority Date: 03/16/1982
• Status: Expired due to Fees

• Current Assignee: Siemens Nixdorf Informationssysteme AG (Siemens AG)
• Original Assignee: Siemens AG
• Inventors: Schlenk, Manfred
• Primary Examiner(s): Krawczewicz, Stanley T.
• Assistant Examiner(s): Solis, Jose M.
• Application Number:
  US06/465,117
• Time in Patent Office: 909 Days
• Field of Search: 340/662, 340/663, 340/660, 340/654, 340/664, 361/86, 324/51, 307/200 A
• US Class Current: 324/537
• CPC Class Codes: G01R 19/145 Indicating the presence of current or voltage
• CPC Class Codes: H02H 1/0053 Means for storing the measured quantities during a predetermined time

Abstract

A circuit arrangement detects and stores power line faults. The occurrence of sporadic faults as represented, for example, by inadmissibly long network collapses, which could lead to shut-down of a current supply and, therefore, to downtime of a computer are generally difficult to detect because the faults disappear given a return of the network, as does, therefore, the prerequisite for detecting the cause of such faults. For the purpose of detecting the cause of the fault, the rectified power line voltage is supplied to a comparison circuit followed by a signal circuit. The signal circuit is connected to a memory which influences a display. As a result, power line faults remain stored despite the return of the power line input voltage. The circuit arrangement is particularly suitable for use in power supply systems for data processing devices.

Claims

1. A circuit arrangement for detecting and storing power line faults, comprising:

a rectifier for connection to a power line and rectifying the power line voltage;

a comparison circuit connected to a reference voltage and to said rectifier for comparing the rectified voltage to the reference voltage and producing a predetermined voltage when the rectified voltage falls below the reference voltage;

a memory connected to said comparison circuit and responsive to the predetermined voltage to assume a predetermined storage state and including an inhibit input for receiving an inhibit signal during a start-up mode for disconnecting the arrangement between start-up so that an error display occurs; and

display means connected to said memory and operable in response to said predetermined storage state.

2. The circuit arrangement of claim 1, wherein:

said comparison circuit comprises an operational amplifier including an inverting input, a non-inverting input and an output, a Wheatstone bridge connected to said rectifier and including a first output connected to said non-inverting input and a second output connected to said inverting input, said Wheatstone bridge further comprising a Zener diode in one arm thereof and connected to said second output for producing the reference voltage;

said memory comprises a monoflop connected to and driven by said operational amplifier, said monoflop including said inhibit input for receiving an inhibit signal during a start-up mode, and a bistable relay connected to and driven by said monoflop, said bistable relay including relay contacts and a reset input for receiving a reset signal; and

said display means comprises a light-emitting diode for connection to an energizing source via said relay contacts.