Coded data on a record carrier and method for encoding same
First Claim
1. A method for encoding digital data which is recorded in arcuate tracks without timing or synchronization data on a planar substrate to form a data record carrier with a plurality of arcuate tracks thereon, each track being spaced from an adjacent track by a predetermined distance along a common centerline of the tracks, each track having the same radius throughout the arcuate path of said track such that each track extends in an arcuate manner across the data record carrier and is arranged in a nested manner relative to adjacent tracks along said common centerline, each track having a plurality of data cells therein and each track having a front track address section, a back track address section and groups of encoded data bits referred to as coded groups therebetween, each cell having the same cell length in the direction of each track for each bit of data stored in each cell and having the same cell width in a direction tranverse to the direction of each track, each cell for one form of logic (0 or 1) being a non-transition cell and each cell for the other form of logic (1 or 0) being a transition cell, said method of encoding providing error correction and including the steps of:
- providing in each coded group a plurality of coded words, each word comprising a byte of data bits and a field of parity bits for error correction.
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Accused Products
Abstract
The coded data (12) on the record carrier (10) and the method for encoding such data (12) in tracks (14) provide a relatively simple and yet very effective means for making the data record carrier (10), and particularly the data (12) recorded thereon, highly tolerant of errors such as "burst errors" where one or more spots of data on the data record carrier (10) are obliterated. The data (12) is recorded on the data record carrier (10) in arcuate nested tracks (14), each track (14) comprising a stream of data bits. The stream of data bits includes an encoded front track address (32) and encoded back track address (44) with coded groups or so-called Hamming type coded groups (52) of data bits therebetween each of which can comprise 96 or 105 data bits. Error correction is provided by including in the coded groups data words which include a data byte and a field of parity bits, typically an eight bit data byte followed by a four bit parity field. Also a cyclic redundancy checksum byte is provided in the group as a further check of the data therein. Further, this data is multiplexed. Additionally, one or two redundant groups are provided in each track (14) for recreating missing groups and a cyclic redundancy checksum field is provided for error detection in each track (14).
51 Citations
73 Claims
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1. A method for encoding digital data which is recorded in arcuate tracks without timing or synchronization data on a planar substrate to form a data record carrier with a plurality of arcuate tracks thereon, each track being spaced from an adjacent track by a predetermined distance along a common centerline of the tracks, each track having the same radius throughout the arcuate path of said track such that each track extends in an arcuate manner across the data record carrier and is arranged in a nested manner relative to adjacent tracks along said common centerline, each track having a plurality of data cells therein and each track having a front track address section, a back track address section and groups of encoded data bits referred to as coded groups therebetween, each cell having the same cell length in the direction of each track for each bit of data stored in each cell and having the same cell width in a direction tranverse to the direction of each track, each cell for one form of logic (0 or 1) being a non-transition cell and each cell for the other form of logic (1 or 0) being a transition cell, said method of encoding providing error correction and including the steps of:
- providing in each coded group a plurality of coded words, each word comprising a byte of data bits and a field of parity bits for error correction.
- View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46. A method for encoding digital data which is recorded in arcuate tracks without timing or synchronization data on a planar substrate to form a data record carrier with a plurality of arcuate tracks thereon, each track being spaced from an adjacent track by a predetermined distance along a common centerline of the tracks, each track having the same radius throughout the arcuate path of said track such that each track extends in an arcuate manner across the data carrier and is arranged in a nested manner relative to adjacent tracks along said common centerline, each track having a plurality of data cells therein and each track having a front track address section, a back track section and groups of encoded data bits referred to as coded groups therebetween, each cell having the same cell length in the direction of each track for each bit of data stored in each cell and having the same cell width in a direction transverse to the direction of each track, each cell for one form of logic (0 or 1) being a non-transition cell and each cell for the other form of logic (1 or 0) being a transition cell, said method of encoding providing error detection and/or correction of a track address in the front track address section and/or the back track address section and including the steps of:
- providing, in at least one of the front or back track address sections, bit positions twice the number of bit positions in the track address, placing the track address bits in the proper order in the first half of the bit positions in that track address section and placing an inversion or compliment of the address in reverse order in the remaining bit positions in that track address section.
- 47. A data record carrier having digital data encoded in a plurality of arcuate tracks without timing or synchronization data on a planar substrate, each track being spaced from an adjacent track by a predetermined distance along a common centerline of the tracks, each track having the same radius throughout the arcuate path of said track such that each track extends in an arcuate manner across the data record carrier and is arranged in a nested manner relative to the adjacent tracks along said common centerline, each track having a plurality of data cells therein and each track having a front track address section, a back track address section and groups of encoded data bits referred to as coded groups therebetween, each cell having the same cell length in the direction of each track for each bit of data stored in each cell and having the same cell width in a direction transverse to the direction of each track, each cell for one form of logic (0 or 1) being a non-transition cell and each cell for the other form of logic (1 or 0) being a transition cell and each coded group having error correction coded therein such that each coded group comprises a plurality of coded words and each word comprises a byte of data bits and a field of parity bits for error correction.
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73. A data record carrier having digital data encoded in a plurality of arcuate tracks without timing or synchronization data on a planar substrate, each track being spaced from an adjacent track by a predetermined distance along a common centerline of the tracks, each track having the same radius throughout the arcuate path of said track such that each track extends in an arcuate manner across the data record carrier and is arranged in a nested manner relative to adjacent tracks along said common centerline, each track having a plurality of data cells therein and each track having a front track address section, a back track address section and groups of encoded data bits referred to as coded groups therebetween, each cell having the same cell length in the direction of each track for each bit of data stored in each cell and having the same cell width in a direction transverse to the direction of each track, each cell for one form of logic (0 or 1) being a non-transition cell and each cell for the other form of logic (1 or 0) being a transition cell a track address being encoded in said front or back address section by having in at least one of the front or back track address sections, bit positions equal to twice the number of bit positions in the track address, with the track address bits placed in proper order in the first half of the bit positions in said front or back track address section and with an inversion or compliment of the track address bits placed in reverse order in the remaining bit positions in said front and back address section.
Specification