Differential receiver with self-adaptive hysteresis

• US 4,535,294 A
• Filed: 02/22/1983
• Issued: 08/13/1985
• Est. Priority Date: 02/22/1983
• Status: Expired due to Term

• Current Assignee: United Technologies Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Original Assignee: United Technologies Corporation (Raytheon Technologies Corporation d/b/a RTX)
• Inventors: Ericksen, James P., Stack, Timothy F.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US06/468,613
• Time in Patent Office: 903 Days
• Field of Search: 307/351, 307/358, 307/359, 307/290, 307/475, 307/261, 328/151, 328/162, 328/163, 328/135, 328/150
• US Class Current: 327/58
• CPC Class Codes: H03F 2200/351 Pulse width modulation being used in an amplifying circuit
• CPC Class Codes: H03K 3/02337 Bistables with hysteresis, e.g. Schmitt trigger non-regenerative amplitude discriminators G01R19/165
• CPC Class Codes: H03K 5/084 modified by switching, e.g. by a periodic signal or by a signal in synchronism with the transitions of the output signal

Abstract

A conventional regenerative comparator is modified by including a transistor switch in the feedback network to open circuit the feedback path according to the output state of the comparator, and by biasing the noninverting input of the comparator with a voltage directly proportional to the amplitude of the input signal, thereby providing variable threshold comparator with a hysteresis transfer characteristic with two distinct state change threshold levels that are a fixed ratio of the amplitude of the input signal.

Claims

1. Apparatus for providing unipolar conditioned output signal manifestations of a varying peak-to-peak amplitude bipolar input signal, comprising:

differential amplifier input means having two input nodes, responsive to the bipolar input signal at said input nodes for providing at an output node a bipolar first conditioned signal representative of the input signal having common mode noise rejected;

peak detector means responsive to said first conditioned signal for providing a bias voltage signal at an output node thereof at a present magnitude directly proportional to a present peak amplitude of said first conditioned signal;

summing means, responsive to said first conditioned signal and to said bias voltage signal for summing said first conditioned signal and said bias voltage signal thereby converting said first conditioned signal to a unipolar second conditioned signal;

comparator means, having a two-state output signal and having noninverting and inverting signal inputs with said inverting signal input responsive to said second conditioned signal and with said noninverting signal input responsive to said bias voltage signal at a first gain value in the presence of a first output state caused by a noninverting signal input magnitude greater than an inverting signal input magnitude and responsive to said bias voltage signal at a second gain value in the presence of a second output state caused by an inverting signal input magnitude greater than a noninverting signal input magnitude;

inverter means, responsive to said two-state output signal for providing inverted first and second output state signals;

switching means, responsive to said inverted first and second output state signals for providing a conditioned output signal and for providing an effective ground path at a switched output node thereof in the presence of said inverted second output state and for opening said effective ground path in the presence of said inverted first output state;

variable voltage divider means, having three resistive legs with a common node connected to said noninverting input and having a first leg connected to said peak detector output node, a second leg connected to ground, and a third leg connected to said switching means'"'"' switched output node, said variable voltage divider means responsive to the switched state of said switching means for providing a voltage dividing network having said first leg in series with said second leg only in the presence of said inverted first output state and having said first leg in series with said second and third legs in parallel in the presence of said inverted second output state; and

signal level translator means, responsive at a first input to said conditioned output signal and responsive at a second input to said bias voltage signal for translating said conditioned output signal to a conditioned output signal manifestation compatible with TTL logic.