Method and apparatus for addressing a peripheral interface by mapping into memory address space

• US 4,535,404 A
• Filed: 04/29/1982
• Issued: 08/13/1985
• Est. Priority Date: 04/29/1982
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Shenk, William H.
• Primary Examiner(s): Heckler, Thomas M.
• Assistant Examiner(s): Dorsey, Daniel K.
• Application Number:
  US06/373,062
• Time in Patent Office: 1,202 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/59
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 12/063 for I/O modules, e.g. memory mapped I/O I/O protocol G06F13/42
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device

Abstract

A method and apparatus for addressing a peripheral interface by mapping into the memory address space of a processor contained in a peripheral controller. The processor in the peripheral controller initializes interface logic within the peripheral controller and in the host system peripheral interface logic to which the peripheral controller is attached to either transmit or receive a block of data. Once initialized, units of data are transmitted across the interface between the peripheral controller and host system using a strobe and acknowledge signal to indicate when data can be taken or placed on data lines. The processor is placed in a wait state as each unit of data is transferred and a watch dog timer is provided to detect any transfer that is not completed within the normal response time of the interface.

Claims

1. An apparatus for transferring information across an interface between a first subsystem and a second subsystem of a system, wherein said first subsystem includes a programmable processor and a memory, said processor capable of executing memory reference instructions which reference by a memory address data stored in said memory, said apparatus comprising:

A. address decoding means coupled to said processor, said address decoding means for detecting said memory address of said memory reference instructions which address a predetermined memory location in said memory;

B. interface control means coupled to said address decoding means and said processor, said interface control means responsive to said address decoding means when said address decoding means detects said memory reference instruction being executed which addresses said predetermined memory location for generating a strobe signal to said second subsystem and for receiving an acknowledge signal from said second subsystem;

C. a wait means coupled to said interface control means and said processor, said wait means responsive to said interface control means for generating a wait signal to place said processor in a wait state at the time said interface control means generates said strobe signal and for removing said processor from said wait state upon receipt of said acknowledge signal by said interface control means from said second subsystem; and

D. transceiver means coupled to said interface control means, said processor and said second subsystem, said transceiver means for receiving data from said processor during the execution of said write memory reference instruction and transmitting the data to said second subsystem and for receiving data from said second subsystem and transmitting the data to said processor during the execution of said read memory reference instruction

whereby said first subsystem can transfer information to or from said second subsystem by said processor executing memory reference instructions addressing said predetermied memory locations thereby effectively mapping said interface into the address space of said memory.

2. The apparatus as claimed in claim 1 wherein said wait means further includes a watch dog timer means coupled to said processor, said watch dog timer means for counting a predetermined number of processor clock cycles which occur after said strobe signal is generated by said interface control means but before said interface control means receives said acknowledge signal from said second subsystem, said watch dog timer means for generating an interrupt to said processor if said predetermined number of clock cycles is exceeded before said watch dog timer means is reset in response to said wait means receiving a completion signal from said interface control means.

3. The apparatus as in claim 2 wherein said wait means further includes reset means for resetting said wait signal in response to a timeout signal from said watch dog timer means indicating that said predetermined number of clock cycles has elapsed or a transfer complete signal from said interface control means indicating that said interface control means has received said acknowledge signal from said second subsystem whereby said processor can complete the execution of the memory reference instruction which caused the data to be transmitted across said interface.

4. The apparatus as in claim 1 wherein said first said subsystem further comprises an address bus and a data bus and wherein said address bus is coupled to said processor, said memory and said address decoding means and wherein said data bus is coupled to said processor, said memory, said transceiver means, and said interface control means.

5. The apparatus as in claim 1 wherein said processor is a microprocessor.

6. The apparatus as in claim 1 wherein said memory is a dual ported memory.

7. The apparatus as in claim 1 wherein first said subsystem is a peripheral controller and said second subsystem is a host data processing system.

8. The apparatus as in claim 1 wherein said first subsystem is a host data processing system and wherein said second subsystem is a peripheral controller.

9. The apparatus as in claim 1 wherein second said subsystem comprises a second memory, an incrementing address register means, and a control means, said second memory coupled to said incrementing address register means, said incrementing address means coupled to said control means, said transceiver means coupled to said second memory, said incrementing address register means and said control means, said control means coupled to said interface control means, said second memory for receiving or transmitting data from or to said transceiver means, said incrementing address register means for specifying the location in said second memory where said information is to be read from or written into said second memory, said control means for indicating to said incrementing address register means when to increment an address stored in said incrementing address register means, said control means for generating said acknowledge signal to said interface control means when said information has been received from or transmitted to said transceiver means in response to said control means receiving said strobe signal from said interface control means.

10. The apparatus as in claim 9 wherein said address decoding means further includes means for detecting an input/output instruction which addresses a predetermined input/output port and wherein said interface control means further includes means for setting the state of control lines coupled to said second subsystem and said interface control means to a state as determined by bits of data receiving from said processor.

11. A method for transferring information across an interface between a first subsystem and a second subsystem of a system, wherein said first subsystem includes a programmable processor, an interface control means and a memory, said processor capable of executing memory reference instructions which reference data stored in said memory by a memory address, said method comprising the steps of:

1. detecting the execution of a memory reference instruction which addresses a predetermined memory location in said memory by use of an address decoding means coupled to said processor;

2. indicating to said second subsystem whether data is to be transmitted from said first subsystem to said second subsystem or from second subsystem to said first subsystem as a function of whether a write or a read memory reference instruction is being executed by said processor;

3. generating a strobe signal to said second subsystem in response to said address decoding means detecting the execution of said memory reference instruction which addresses said predetermined memory location;

4. placing said processor in a wait state in response to a wait signal received from said interface control means when said interface control means generates said strobe signal;

5. waiting for receipt of an acknowledge signal from said second subsystem by said interface control means, said acknowledge signal being generated by said second subsystem in response to said second subsystem receiving data from or transmitting data to said first subsystem;

6. transmitting data from said processor to said second subsystem across said interface if said write memory reference instruction is being executed by said processor;

7. receiving information from said second subsystem and transferring it to said processor if said read memory reference instruction is being executed by said processor upon receipt of said acknowledge signal from said second subsystem;

8. removing said processor from said wait state upon receipt by said interface control means of said acknowledge signal from said second subsystem; and

13. The method of claim 11 wherein during step 5 while waiting for said acknowledge signal from said second subsystem, a timing operation is performed which counts the number of processor clock cycles which have elapsed since the generation of said strobe signal and wherein if the number of clock cycles exceeds a predetermined number an interrupt is generated to said processor and said processor is removed from said wait state to enable processing of said interrupt by said processor.

12. continuing the execution of said processor memory reference instructions

whereby said first subsystem can transfer information to or from second subsystem by said processor executing memory reference instructions addressing said predetermined memory locations thereby effectively mapping said interface into the address space of said memory.

14. A method for transferring information across an interface between a first subsystem and a second subsystem of a system wherein said first subsystem includes a programmable processor and a first memory, said processor capable of executing memory reference instructions which reference data stored in said first memory by a memory address, said method comprising the steps of:

1. setting a control/data line to a control state and a direction line to an out state by executing an I/O instruction to a predetermined I/O port address;

2. sending a direct memory access select information to said second subsystem by referencing a predetermined memory location in said first memory;

3. setting said control/data line to a data state and said direction line to the out state by executing an input/output operation to said predetermined I/O port address;

4. sending the address of a first location of a block of memory locations in a second memory contained in said second subsystem to said second subsystem by executing a memory reference instruction addressing said predetermined memory address;

5. initializing a pointer to a first location in said first memory;

15. loading a counter with a count of the number of units of data to be transferred between said first subsystem and said second subsystem;

7. if a write operation is to be performed from said first subsystem to said second subsystem, accessing the next unit of data in the said first memory and executing a memory reference instruction addressing said predetermined memory location or, if a read operation is to be performed from said second subsystem to said first subsystem, executing a memory reference instruction addressing said predetermined memory location and writing said received unit of data into the next memory location addressed by said pointer to said first memory;

8. incrementing said pointer;

9. decrementing the count of the number of units of data to be transferred;

10. returning to step 7, if all units of data have not been transferred between said first subsystem and second subsystem; and

16. continuing, if all units of data have been transferred;

whereby said first subsystem can transfer information to or from said second subsystem by said processor executing memory reference instructions addressing said predetermined memory locations thereby effectively mapping said interface into the address space of said first memory.