Control of serial memory

• US 4,535,427 A
• Filed: 12/06/1982
• Issued: 08/13/1985
• Est. Priority Date: 12/06/1982
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: Mostek Corporation (Rtx Corporation)
• Inventors: Jiang, Ching-Lin
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/447,348
• Time in Patent Office: 981 Days
• Field of Search: 365/190, 365/205, 365/189, 365/230
• US Class Current: 365/205
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

A FIFO memory chip includes read and write pointers in the form of an X and a Y shift register carrying a pair of pointer bits that point to a memory cell in a rectangular cell array.

Claims

1. An integrated circuit serial memory comprising:

an array of memory cell elements;

writing means for writing data sequentially into said array;

reading means for reading data sequentialy out of said array; and

control means for setting flags indicating memory-full and memory-empty states;

characterized in that;

said array comprises a two dimensional array of non-shifting memory cells, having an X and a Y dimension;

said writing means includes a first write shift register carrying a first write pointer bit along the X dimension of said array and a second write shift register carrying a second write pointer bit along the Y dimension of the array, which first and second write shift register pointer bits point in the X and Y dimensions to a write cell; and

said reading means includes a first read shift register carrying a first read pointer bit along the X dimension of said array and a second read shift register carrying a second read pointer bit along the Y dimesion of said array, which first and second read shift register pointer bits point in the X and Y dimensions to a read cell.

2. An integrated circuit serial memory according to claim 1, further characterized in that:

said serial memory is a first-in/first-out memory, whereby said reading means reads sequentially data written by said writing means, beginning with the first to be written data.

3. An integrated circuit memory according to claim 2, further characterized in that:

each of said memory cell elements comprises at least one bit cell for storing a data bit.

4. An integrated circuit memory according to claim 3, further characterized in that:

said bit cell includes dual port means for independently reading data from and writing data into said bit cell.

5. An integrated circuit memory according to claim 2, further characterized in that:

said control means includes means for communicating with other memory chips in a loop memory configuration, whereby write and read operations follow consecutively from a first chip to a second chip, and also in that;

said control means includes means for inhibiting write operations in a full memory chip and for enabling write operations in an adjacent memory chip.

6. An integrated circuit serial memory according to claim 4, in which said dual port means includes a read control line for controlling at least one read access means for establishing a current path from at least one data line to said bit cell and a write control line for controlling at least one write access means, independent of said read access means, for establishing a current path form said at least one data line to said bit cell.