Dual bus communication system

• US 4,535,448 A
• Filed: 12/10/1982
• Issued: 08/13/1985
• Est. Priority Date: 12/10/1982
• Status: Expired due to Term

• Current Assignee: Avaya Technology Corporation Miami Lakes FLA US
• Original Assignee: AT&T, Inc.
• Inventors: Baxter, Leslie A., Brown, Sanford S.
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/448,771
• Time in Patent Office: 977 Days
• Field of Search: 370/94, 370/85, 370/92, 370/60, 370/80
• US Class Current: 370/364
• CPC Class Codes: H04L 12/28 characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks] wireless communication networks H04W ; arrangements for dividing the transmission path H04W40/00
• CPC Class Codes: H04L 12/64 Hybrid switching systems

Abstract

A dual set of busses is used to provide close coupling between the data and voice services of the CS300 communication system. One of these busses is a time division multiplex bus arranged for communication between port access circuits, and the other bus is a packet-switched data processing bus used for interfacing both with the system peripherals and with the port access circuits. The port access circuits, as well as the faster peripheral circuits, can be connected to either or both busses thereby allowing for the efficient easy interchange of information.

Claims

1. In a communication system, a time division bus arranged to interconnect a plurality of communication circuit boards for intercommunication among said circuit boards in established time slots on said time division bus, said time division bus characterized in that data communicated on said bus is routed by the time slot relationship of said data on said time division,

a packet-switched bus arranged for intercommunication in bursty fashion among said plurality of communication circuit boards, said packet-switched bus characterized in that data communicated on said bus is routed in accordance with information contained within said data on said packet-switched bus,

means for connecting certain of said circuits directly to said time division bus, certain of said circuits directly to said packet-switched bus, and certain of said circuits directly and concurrently to both of said busses, and wherein said communication circuits are contained within one or more circuit board housings, each circuit board housing having multiple positions therein for the placement of said communication circuit boards and wherein any of said communication circuit boards may be placed in any of said positions while still having said direct connection to either or both of said busses and wherein each of said busses includes a multipath cable having a termination for each said path at each said position of each said housing, and wherein said circuits which are connectable to both of said busses include means for receiving first data from one of said busses and for delivering second data to the other one of said busses in response to receipt of said first data.

2. In a communication system, a time division bus arranged to interconnect a plurality of communication circuits for intercommunication among said circuits in established time slots on said time division bus, said time division bus is characterized in that the bandwidth of said bus is allocated for the duration of any connection,

a packet-switched bus arranged for intercommunication in bursty fashion among said plurality of communication circuits, said packet-switched bus is characterized in that the bandwidth of said bus is allocated on a demand basis only, and

means for connecting certain of said circuits directly to said time division bus, certain of said circuits directly to said packet-switched bus, and certain of said circuits directly and concurrently to both of said busses, and wherein some of said circuits interface with communication equipment and wherein some of said circuits interface with common resource circuits,

means for communicating information between said communication equipment interface circuits and said common resource circuits over said time division bus, and

wherein at least one of said common resource circuits includes means for modifying said information, and

means for communicating said modified information between said common resource circuits over said packet-switched bus.

3. A communication system comprising

a plurality of interface circuits adapted for interfacing between said system and communication equipment for the transfer of information therebetween, each said interface circuit connectable to a communication bus in a specialized fashion,

a plurality of shared resource circuits available for connection to any of said interface circuits,

a first bus having time slots established thereon, said time slots assignable for the transfer of information between any of said interface circuits and other interface circuits and for the transfer of information between any of said interface circuits and said resource circuits, said time division bus characterized in that data communicated on said bus is routed by the time slot relationship of said data on said time division bus, and

a second bus having packet-switched capability for the transfer of first information between any one resource circuit and a selected other resource circuit over said second bus while second information dependent upon said first information is concurrently being transferred between said one of said resource circuits and an interface circuit over said first bus, said packet-switched bus characterized in that data communicated on said bus is routed in accordance with information contained within said data on said packet-switched bus.

4. The invention set forth in claim 3 wherein said interface circuits are contained within housings each housing having multiple prewired positions therein for the semipermanent placement of said interface circuits and wherein any of said interface circuits may be placed in any of said positions while still having access to either or both of said busses without changing said prewiring between said positions.

5. A communication system comprising

a circuit board housing having a plurality of positions for the insertion of circuit boards, each position having a number of individual paths,

a plurality of interface circuits adapted for interfacing between said system and communication equipment for the transfer of information therebetween, said interface circuits contained on certain of said circuit boards and insertable into said housing at any of said positions thereof,

a plurality of shared resource circuits contained on others of said circuit boards and insertable into said housing at any of said positions thereof,

a first bus interconnecting like paths of each of said positions, said bus having time slots established thereon, said time slots assignable for the transfer of information between any of said housing positions having interface circuits inserted thereat and other housing positions having interface circuits inserted thereat and for the transfer of information between any of said housing positions having interface circuits inserted thereat and housing positions having resource circuits inserted thereat, said time division bus characterized in that data communicated on said bus is routed by the time slot relationship of said data on said time division bus,

a second bus interconnecting like paths of each of said positions, said bus having packet-switched capability for the transfer of information between interface circuit at selected housing positions while information is concurrently being transferred to or from said selected housing positions over said first bus, said packet-switched bus characterized in that data communicated on said bus is routed in accordance with information contained within said data on said packet-switched bus, and

wherein said information transferred over said first bus between a first resource circuit and an interface circuit includes speech signals, and

wherein said first resource circuit includes means for modifying speech signals transferred thereto over said first bus and for placing said modified speech signals on said second bus.

6. The invention set forth in claim 5 wherein at least one of said resource circuits includes means for packaging information transferred from an interface circuit over said first bus for presentation over said second bus to a processor in packet form.

7. In a communication system, a time division bus arranged to interconnect a plurality of communication circuits for intercommunication among said circuits in established time slots on said time division bus, said time division bus characterized in that data communicated on said bus is routed by the time slot relationship of said data on said time division bus,

a packet-switched bus arranged for intercommunication in bursty fashion among said plurality of communication circuits, said packet-switched bus characterized in that data communicated on said bus is routed in accordance with information contained within said data on said packet-switched bus,

means for allowing each said circuit direct access concurrently to both of said busses, and

wherein some of said circuits interface with communication equipment and wherein some of said circuits interface with common resource means,

means for communicating information between said communication equipment interface circuits and said common resource circuits over said time division bus,

means for communicating information between said selected common resource circuits over said packet-switched bus concurrently with the communication of information between said selected common resource circuits and a communication equipment interface circuit, and

at least one of said resource circuits comprising means for receiving data from one of said busses and in response thereto placing data on the other of said busses.

8. In a communication system, a first bus arranged to interconnect a plurality of communication circuits for intercommunication among said circuits in a first manner where data is delivered in accordance with its time relationship with other data on said bus,

a second bus arranged to interconnect a plurality of communication circuit boards in a second manner where data is delivered in accordance with address data associated with said delivered data,

means for connecting certain of said circuits directly to said first bus, certain of said circuits directly to said second bus, and certain of said circuits directly and concurrently to both of said busses, and wherein said circuits which are connectable to both of said busses include means for receiving first data from one of said busses and for delivering second data to the other one of said busses in response to receipt of said first data.