Signal detection apparatus

• US 4,535,459 A
• Filed: 05/26/1983
• Issued: 08/13/1985
• Est. Priority Date: 05/26/1983
• Status: Expired due to Term

• Current Assignee: Alcatel Network Systems India Limited (Nokia Corporation)
• Original Assignee: Rockwell International Corporation
• Inventors: Hogge, Charles R. Jr.
• Primary Examiner(s): Griffin, Robert L.
• Assistant Examiner(s): Chin, Stephen
• Application Number:
  US06/498,385
• Time in Patent Office: 810 Days
• Field of Search: 375/80, 375/81, 375/82, 375/119, 375/120, 331/1 A, 331/17, 331/34, 331/DIG. 2, 328/133, 329/104, 360/41, 307/516
• US Class Current: 375/324
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals
• CPC Class Codes: H03L 7/089 the phase or frequency detector generating up-down pulses H03L7/087 takes precedence
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A phase detection function is obtained by performing two series retiming operations on a data input signal in accordance with a local clock and exclusive OR'"'"'ing the signals involved in the two retiming operations. The first exclusive OR'"'"'ing provides a variable pulse width signal and the second exclusive OR'"'"'ing provides a fixed pulse width signal which may be used as a reference. The combination of the two signals can then be used to provide an indication of phase of the clock with respect to the data. By taking the phase detected signal and supplying it in integrated format to a VCO and using the output of the VCO to provide the clock input to the retiming means, a circuit is provided which provides not only data regeneration, but also clock recovery from the data input and assures that the leading edge of the recovered clock is centered between positive going and negative going transitions of the data to be regenerated. This regeneration can take place in the form of jitter reduction, pulse amplitude restore and pulse width restore. The same circuitry can also, through the addition of one feedback loop, provide data equalization.

Claims

1. Phase detector means comprising, in combination:

data signal input means for supplying input data;

first D flip-flop means, including D and C (clock) input terminal means and Q output terminal means;

second D flip-flop means, including D and C (clock) input terminal means and Q output terminal means;

first EOR (exclusive OR) means, including input means and output means, connected to receive input signals at said input means thereof from the D and Q terminal means of said first flip-flop means

second EOR (exclusive OR) means, including input means and output means, connected to receive input signals at said input means thereof from the D and Q terminal means of said second flip-flop means

means connecting said data signal input means to said D input terminal means of said first flip-flop means;

means connecting said Q output terminal means of said first flip-flop means to said D input terminal means of said second flip-flop means;

first and second integrating means, each including input means and output means, connected to said output means of said first and second EOR means for receiving input signals therefrom;

VCO (controlled variable frequency oscillator) means, including input means and first and second opposite phase signal output means, connected to said output means of said first and second integrator means for receiving output signals therefrom, said VCO means varying in frequency as a function of the sum of the signals received from said first and second integrator means;

means connecting said first and second output means of said VCO to said C input means of said first and second D flip-flop means respectively; and

means for outputting retimed data from the Q output terminal means of said second flip-flop means.

2. The method of synchronously regenerating a data signal comprising the steps of:

passing the data signal through a series connection D type flip-flops each including D, C and Q terminals;

exclusive ORing the signals appearing at the D and Q terminals of each of the two D flip-flops;

differentially integrating and summing the results of the exclusive ORing to provide a control voltage;

generating a variable frequency output signal in response to the value of said control voltage; and

clocking the C terminals of said D flip-flops as a function of said variable frequency output signal.

3. The method of simultaneously recovering a clock signal and regenerating a data signal comprising the steps of:

passing the data signal through a series connection of two D type flip-flops each including D, C and Q terminals;

exclusive ORing the D and Q terminal signal outputs of each of the two D flip-flops;

differentially integrating and summing the results of the exclusive ORing to provide a control voltage;

generating a variable frequency output signal in response to the value of said control voltage; and

clocking the C terminals of said D flip-flops as a function of said variable frequency output signal.

4. Apparatus for regenerating a data signal comprising, in combination:

means for supplying data to be regenerated;

means for passing said data through a series connection of two D type flip-flops each including D, C and Q terminal means;

means for exclusive ORing the signals appearing at the D and Q terminal means of each of the two D type flip-flops;

means for differentially integrating and summing the results of the exclusive ORing to provide a control voltage;

means for generating a variable frequency output signal in response to the value of said control voltage; and

means for supplying clock signals to the C terminals of said D flip-flops as a function of said variable frequency output signal.

5. Apparatus for simultaneously recovering a clock signal and regenerating a data signal comprising the steps of:

means for passing the data signal through a series connection of two D type flip-flops each including D, C and Q terminals;

means for exclusive ORing the signals appearing at the D and Q terminals of each of the two D flip-flops;

means for differentially integrating and summing the results of the exclusive ORing to provide a control voltage;

means for generating a variable frequency output signal in response to the value of said control voltage; and

means for clocking the C terminals of said D flip-flops as a function of said variable frequency output signal.

6. Phase detector means comprising, in combination:

first means for retiming an incoming data signal in accordance with a local clock signal to produce a first retimed data signal;

second means for retiming said first retimed data signal in accordance with said local clock signal to produce a second retimed data signal;

third means for exclusive ORing said incoming data signal with said first retimed data signal to produce a variable width control signal indicative of phase; and

fourth means for exclusive ORing said first retimed data signal with said second retimed data signal to produce a fixed width reference signal.

7. Combined data detection, data signal regeneration and clock recovery apparatus using the apparatus of claim 6 and comprising, in addition:

controlled variable frequency oscillator means connected to said third and fourth means for receiving said variable width control signal and said fixed width reference signal therefrom, the frequency of said variable frequency oscillator changing as a function of the integrated and summed values of the received signals; and

means for generating two opposite phase clock signals from the signal output by said oscillator means and applying same to clock said first and second means respectively.

8. Clock recovery apparatus using the apparatus of claim 6 and comprising, in addition:

controlled variable frequency oscillator means connected to said third and fourth means for receiving said variable width control signal and said fixed width reference signal therefrom, the frequency of said variable frequency oscillator changing as a function of the integrated and summed values of the received signals; and

means for generating two opposite phase clock signals from the signal output by said oscillator means and applying same to clock said first and second means respectively.

9. Data detection apparatus using the circuitry of claim 6 and comprising, in addition:

controlled frequency oscillator means connected to said third and fourth means for receiving said variable width control signal and said fixed width reference signal therefrom, the frequency of said controlled frequency oscillator changing as a function of the integrated and summed values of the received signals; and

means for generating two opposite phase clock signals from the signal output by said oscillator means and applying same to clock said first and second means respectively.

10. Combined data detection, data signal regeneration and clock recovery apparatus using the apparatus of claim 6 and comprising, in addition:

controlled variable frequency oscillator means connected to said third and fourth means for receiving said variable width control signal and said fixed width reference signal therefrom, the frequency of said variable frequency oscillator changing as a function of the integrated and summed values of the received signals;

means for generating two opposite phase clock signals from the signal output by said oscillator means and applying same to clock said first and second means respectively; and

means for delaying and inverting said second retimed data signal and summing the result with said incoming data signal in a feedback manner to equalize data being passed.