Random timer
First Claim
Patent Images
1. A timer system comprising:
- a clock providing pulses at a given frequency on a clock output lead, a first counter having a clock input connected to the clock output lead, the first counter having N stages continuously recycling, a digital noise generator, a second counter having a clock input connected to an output of the digital noise generator so that its outputs are sequentially high at a random frequency, the second counter being connected to continuously recycle, an N-stage shift register having parallel inputs one of which is connected to a fixed potential for a low logic level, the other parallel inputs being connected to different outputs of the second counter, the shift register having a load input connected to one output of the first counter so that the shift register is loaded at its parallel inputs on every Nth clock pulse with an N-bit word having one and only one stage high, the shift register having a clock input connected to the clock output lead so that the word appears bit by bit at a serial output, whereby time is divided into equal intervals with a pulse appearing at said serial output at random within each interval.
1 Assignment
0 Petitions
Accused Products
Abstract
The timer generates a selected number of control pulses per hour, at unpredictable (pseudo-random) intervals, for use with a time lapse video tape recorder used for time studies. The hour is divided into equal intervals to provide the number of samples required per hour, and one trigger pulse is generated randomly timed within each interval. A noise generator drives a counter whose outputs are loaded every Nth clock pulse into an N-stage shift register. The contents of the shift register are shifted out serially at the clock frequency.
-
Citations
1 Claim
-
1. A timer system comprising:
- a clock providing pulses at a given frequency on a clock output lead, a first counter having a clock input connected to the clock output lead, the first counter having N stages continuously recycling, a digital noise generator, a second counter having a clock input connected to an output of the digital noise generator so that its outputs are sequentially high at a random frequency, the second counter being connected to continuously recycle, an N-stage shift register having parallel inputs one of which is connected to a fixed potential for a low logic level, the other parallel inputs being connected to different outputs of the second counter, the shift register having a load input connected to one output of the first counter so that the shift register is loaded at its parallel inputs on every Nth clock pulse with an N-bit word having one and only one stage high, the shift register having a clock input connected to the clock output lead so that the word appears bit by bit at a serial output, whereby time is divided into equal intervals with a pulse appearing at said serial output at random within each interval.
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeUnited States Of America As Represented By The Secretary Of The Air Force
-
Original AssigneeUnited States Of America As Represented By The Secretary Of The Air Force
-
InventorsPalvolgyi, Frank A.
-
Primary Examiner(s)Heyman, John S.
-
Application NumberUS06/521,803Time in Patent Office734 DaysField of Search377/54, 377/109, 377/56, 328/129.1, 331/78, 364/717US Class Current377/54CPC Class CodesH03K 3/84 Generating pulses having a ...
