Method of converting a digital signal into an analog signal and a digital-to-analog converter therefor

• US 4,536,743 A
• Filed: 08/09/1982
• Issued: 08/20/1985
• Est. Priority Date: 08/14/1981
• Status: Expired due to Term

• Current Assignee: Nakamichi Corporation (Nimble Holdings Co. Ltd.)
• Original Assignee: Nakamichi Corporation (Nimble Holdings Co. Ltd.)
• Inventors: Uchikoshi, Gohji
• Primary Examiner(s): Sloyan, T. J.
• Application Number:
  US06/406,214
• Time in Patent Office: 1,107 Days
• Field of Search: 340/347 DA, 340/347 CC, 340/347 M, 377/42, 364/606, 307/265, 328/129.1, 328/130.1, 328/160
• US Class Current: 341/152
• CPC Class Codes: H03M 1/08 of noise H03M1/0617 takes precedence
• CPC Class Codes: H03M 1/82 with intermediate conversion to time interval

Abstract

In the invention, a digital signal consisting of upper and lower bits is sampled while the upper and lower bits are divided. The sampled digital signal components of upper and lower bits are converted into upper and lower pulse width signals having a pulse width responding to their data value, respectively. Thereafter, the upper and lower pulse width signals are mixed and pass through a smoothing filter to convert the digital signal into an analog signal. The upper pulse width signal is formed of a pulse signal varying in a pulse width in response to the data value of the upper bits relative to a center of pulse width which has a fixed time position within a sampling period. The lower pulse width signal is formed of a combination of pulse signals varying in each pulse width in response to the data value of the lower bits relative to each center of pulse width which is at each pulse edge of the upper pulse width signal.

Claims

1. A method of converting a digital signal into an analog signal, said digital signal consisting of upper and lower bit signals having a predetermined weight ratio, comprising the steps of:

converting said upper and lower bit signals into upper and lower pulse width signals, said upper pulse width signal varying in its pulse width corresponding to a data value of said upper bit signal relative to the center of the pulse width being at a fixed time position within a sampling period, while said lower pulse width signal varies in its pulse width corresponding to a data value of said lower bit signal and the centers of each pulse width being at each pulse edge of said upper pulse width signal;

mixing said upper and lower pulse width signals corresponding to said weight ratio to form a composite signal;

and thereafter passing and composite signal through a smoothing filter to demodulate said digital signal into said analog signal.

2. A digital-to-analog converter for converting a digital signal into an analog signal, said digital signal consisting of upper and lower bit signals having a predetermined weight ratio, comprising:

an upper pulse width signal forming circuit to convert said upper bit signal into an upper pulse width signal varying in its pulse width corresponding to a data value of said upper bit signal relative to the center of the pulse width being at a fixed time position within a sampling period;

a lower pulse width signal forming circuit to convert said lower bit signal into a lower pulse width signal varying in its pulse width corresponding to a data value of said lower bit signal and the centers of each pulse width being at each edge of said upper pulse width signal;

a mixer circuit to mix said upper and lower pulse width signals corresponding to said weight ratio to form a composite signal;

and a filter circuit to smooth said composite signal to demodulate said digital signal into said analog signal.

3. A digital-to-analog converter as set forth in claim 2, further comprising a pair of latching circuits to store the upper and lower bit signals, wherein said upper and lower pulse width signal forming circuits comprise set-reset flip-flop circuits, and a plurality of counters being connected between said latching circuits and said set-reset flip-flop circuits.