Bit serial convolutional decoder for VLSI implementation
First Claim
1. A decoder circuit comprising,calculator means (23) for receiving coded symbol signals and producing calculator output signals representative of said symbol signals,said calculator means includes serial-to-parallel converter means for converting said symbol signals to parallel output signals,full adder means connected to said serial-to-parallel converter to receive said parallel output signals and produce said calculator output signals which are representative of said symbol signals,evaluator means (24) for receiving said calculator output signals from said calculator means and producing evaluator output signals which indicate a minimum value of said calculator output signals and are used in establishing the output signals to be produced by the decoder circuit,convergence means (25) for receiving said evaluator output signals from said evaluator means and producing convergence output signals representative of the most probable signal conditions,said convergence means includes multiplexer means connected to receive said evaluator output signals and shift register means connected to receive output signals from said multiplexer means,said shift register means comprises a plurality of shift registers and a plurality of multiplexer devices,one input of each multiplexer device connected to an output of said multiplexer means,another input of each multiplexer device connected to an output the preceding shift register,the output of each multiplexer device connected to an input of the succeeding shift register, andvaluation means (26) for receiving said convergence output signals from said convergence means and producing a decoder output signal representative of the coded symbol signals supplied to said calculator means.
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Accused Products
Abstract
A decoder for forward-error-correcting (FEC) convolutional codes. The decoder uses the Viterbi algorithm for decoding the rate 1/2, constraint length 7 code with generator polynomials x6 +x5 +x3 +x2 +1, and x6 +x3 +x2 +x+1. The architecture of the instant decoder is appropriate for implementation on a single, monolithic VLSI integrated circuit chip and includes a branch metric calculator circuit which produces output signals representative of input symbol signals. These output signals are supplied to a metric update circuit which evaluates the signals from the calculator circuit and provides decisions to a path update circuit which converges the signals thereto and the output signals of which are evaluated by a majority vote circuit which produces data output signals representative of data input signals.
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Citations
14 Claims
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1. A decoder circuit comprising,
calculator means (23) for receiving coded symbol signals and producing calculator output signals representative of said symbol signals, said calculator means includes serial-to-parallel converter means for converting said symbol signals to parallel output signals, full adder means connected to said serial-to-parallel converter to receive said parallel output signals and produce said calculator output signals which are representative of said symbol signals, evaluator means (24) for receiving said calculator output signals from said calculator means and producing evaluator output signals which indicate a minimum value of said calculator output signals and are used in establishing the output signals to be produced by the decoder circuit, convergence means (25) for receiving said evaluator output signals from said evaluator means and producing convergence output signals representative of the most probable signal conditions, said convergence means includes multiplexer means connected to receive said evaluator output signals and shift register means connected to receive output signals from said multiplexer means, said shift register means comprises a plurality of shift registers and a plurality of multiplexer devices, one input of each multiplexer device connected to an output of said multiplexer means, another input of each multiplexer device connected to an output the preceding shift register, the output of each multiplexer device connected to an input of the succeeding shift register, and valuation means (26) for receiving said convergence output signals from said convergence means and producing a decoder output signal representative of the coded symbol signals supplied to said calculator means.
Specification