Integrated logic circuit adapted to performance tests

• US 4,536,881 A
• Filed: 10/27/1983
• Issued: 08/20/1985
• Est. Priority Date: 03/15/1979
• Status: Expired due to Fees

• Current Assignee: Nippon Electric Company Limited (NEC Corporation)
• Original Assignee: Nippon Electric Company Limited (NEC Corporation)
• Inventors: Kasuya, Yoshihiro
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): Davis, B. P.
• Application Number:
  US06/545,608
• Time in Patent Office: 663 Days
• Field of Search: 377/70, 377/72, 377/80, 377/81, 307/445, 324/73 PC
• US Class Current: 377/70
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

An easily testable integrated logic circuit utilizes a plurality of flip-flops to form a feedback shift register. In some embodiments, means are provided for selectively forming the flip-flops into a feedback shift register and for selectively supplying either the flip-flop contents or a random signal as partial inputs to the combinational logic circuit. In other embodiments, the feedback shift register is coupled to the AND logic array outputs of a combinational circuit which also includes and OR logic array.

Claims

1. An easily testable integrated logic circuit, comprising:

a combinational logic circuit receiving a plurality of first inputs and a plurality of second inputs for providing logic outputs;

a feedback shift register having an output and including a plurality of first through n-th series-connected flip-flops each having an input and an output, said flip-flops receiving in parallel at least a portion of said logic outputs from said combinational logic circuit and advancing said outputs in series through said first through n-th flip-flops while feeding an output from at least one of said flip-flops back to the input of another of said flip-flops to thereby compress a signal sequence in said logic outputs, the output of any one of said flip-flops constituting the output of said feedback shift register; and

means for selectively disconnecting the series connection of said flip-flops whereby each of said flip-flops receives and stores a respective one of said portion of said logic outputs received in parallel from said combinational logic circuit, at least a portion of said outputs of said flip-flops being fed back in parallel as said second inputs to said combinational logic circuit when said series connection of said flip-flops is disconnected.

2. An easily testable integrated logic circuit as claimed in claim 1, wherein said logic outputs provided by said combinational logic circuit include first and second groups of logic outputs, said flip-flops receiving in parallel only said second group of logic outputs.

3. An easily testable integrated logic circuit as claimed in claim 2, further comprising means for determining the existence of an error in said combinational logic circuit in accordance with at least said feedback shift register output.

4. An easily testable integrated logic circuit as claimed in claim 1, further comprising means for determining the existence of an error in said combinational logic circuit in accordance with at least said feedback shift register output.

5. An easily testable integrated logic circuit, comprising:

a combinational logic circuit receiving a plurality of first inputs and a plurality of second inputs for providing first and second groups logic outputs;

a feedback shift register having an output and including a plurality of first througn n-th series-connected flip-flops each having an input and an output, said flip-flops receiving in parallel only said second group of said logic outputs from said combinational logic circuit and advancing said outputs in series through said first through n-th flip-flops while feeding an output from at least one of said flip-flops back to the input of another of said flip-flops to thereby compress a signal sequence in said logic outputs, the output of any one of said flip-flops constituting the output of said feedback shift register; and

means for determining the existence of an error in said combinational logic circuit in accordance with said feedback shift register output and said first group of logic outputs from said combinational logic circuit.