Two-gate non-coplanar FET with self-aligned source

• US 4,537,654 A
• Filed: 12/09/1983
• Issued: 08/27/1985
• Est. Priority Date: 12/09/1983
• Status: Expired due to Term

• Current Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Original Assignee: TRW Limited (Zeppelin - Stiftung der Stadt Friedrichshafen)
• Inventors: Nakano, Kenichi, Berenz, John J.
• Primary Examiner(s): Powell, William A.
• Application Number:
  US06/560,075
• Time in Patent Office: 627 Days
• Field of Search: 156/644, 156/653, 156/657, 156/659.1, 156/662, 148/1.5, 148/187, 148/188, 29/571, 29/576 B, 29/580, 427/88, 427/91, 427/85, 430/313, 430/317, 357/22, 357/23, 357/41, 357/65
• US Class Current: 438/176
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/475 on AIII-BV compounds
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A two-gate non-coplanar field-effect transistor and a method for its fabrication. An active semiconductor layer is formed over a stop-etch layer on a substrate of semi-insulating material, such as gallium arsenide, and a via hole is formed from the opposite face of the substrate, through to the stop-etch layer. The via hole is metallized and located from the active-layer side of the device using an electron-beam technique. A two-element gate structure is then formed over the active layer, in approximate alignment with the via hole. Then a source region is ion-implanted into the active layer and into the stop-etch layer, using the positions of the gate elements to self-align the source. Drain contact regions are also formed in the active layer by ion implantation. Contact between the source region and the metallized via hole does not depend on accurate and uniform etching of the via hole. Instead, an opening is etched through the source region to the via hole, and filled with ohmic metal to make good contact with the via hole metallization.

Claims

1. A method of fabricating a non-coplanar field-effect transistor, comprising the steps of:

forming a stop-etch layer on a semiconductor substrate;

forming an active semiconductive layer on the stop-etch layer;

forming a metallized via hole in the substrate;

locating the via hole from the active layer face of the device;

forming a two-element gate on the active layer and centered in approximate alignment with the via hole;

implanting a source region in the active layer and the stop-etch layer, in an area located between the gate elements;

implanting drain contact regions in the active layer;

etching an opening in the source region, to extend through to the metallized via hole; and

depositing metal in the source region opening to establish good contact with the via hole metallization.

2. A method as set forth in claim 1, and further including the step of:

annealing the implanted source region in the stop-etch layer, to diffuse ions laterally and ensure overlap of the source region and the gate elements.

3. A method as set forth in claim 1, wherein said step of implanting a source region includes:

implanting ions into the active layer, in an area slightly shorter in length than the distance between the gate elements; and

then

implanting ions into the stop-etch layer.

4. A method as set forth in claim 3, and further including the step of:

annealing the implanted source region in the stop-etch layer, to diffuse ions laterally and ensure partial overlap of the source region and the gate elements.

5. A method of fabricating a non-coplanar field-effect transistor, comprising the steps of:

forming an active layer on a first face of a substrate;

forming a metallized via hole from the second face of the substrate;

forming two gate elements on the active layer in a substantially symmetrical relationship with the via hole;

implanting two drain contact areas in the active layer;

implanting a source region into the device between but not in contact with the gate elements;

annealing the implanted source region to ensure that it partially overlaps the gate elements;

forming an opening through the source region to the metallized via hole; and

depositing metal in the opening to establish contact between the source region and the metallized via hole.

6. A method of fabricating a non-coplanar field-effect transistor, comprising the steps of:

forming a stop-etch layer of semi-insulating gallium aluminum arsenide on one face of a semiconductor substrate of gallium arsenide;

forming an active n+ semiconductive layer of gallium arsenide on the stop-etch layer;

forming a via hole from the other face of the substrate;

depositing a metal coating on the surface of the via hole;

locating the via hole from the first or epitaxial side of the device;

forming two gate elements on the active layer in approximate alignment with the via hole;

implanting ions to form a source contact region in the active layer, in an area located between the gate elements;

implanting ions to form drain contact regions in the active layer;

implanting ions to form an n+ source region in the stop-etch layer and between the gate elements;

etching an opening in the source region, extending through to the metallized via hole; and

depositing metal in the source region opening to establish good contact with the via hole metallization.

7. A method as set forth in claim 6, wherein:

said steps of implanting ions to form source and drain contact regions in the active layer employs silicon doping ions; and

said step of implanting ions to form an n+ source region employs sulfur doping ions.

8. A method as set forth in claim 6, wherein:

the metal used in coating the via hole and depositing metal in the source region opening in an alloy of gold and germanium.

9. A method as set forth in claim 6, wherein said step of forming gate elements includes:

depositing a refractory metal in a predefined gate area.

10. A method as set forth in claim 9, wherein:

the refractory metal is titanium-tungsten.

11. A method as set forth in claim 6, and further including the step of:

annealing after said step of implanting the source region in the stop-etch layer, to diffuse the implanted ions laterally and form an extended source region in overlapping relationship with the gate elements.

12. A method as set forth in claim 11, wherein:

said steps of implanting ions to form source and drain contact regions in the active layer employs silicon doping ions; and

said step of implanting ions to form an n+ source region employs sulfur doping ions.

13. A method as set forth in claim 11, wherein:

the metal used in coating the via hole and depositing metal in the source region opening is an alloy of gold and germanium.

14. A method as set forth in claim 11, wherein said step of forming gate elements includes:

depositing a refractory metal in a predefined gate area.

15. A method of fabricating a non-coplanar field-effect transistor, comprising the steps of:

forming a stop-etch layer of semi-insulating gallium aluminum arsenide on one face of a semiconductor substrate of gallium arsenide;

forming an active n+ semiconductive layer of gallium arsenide on the stop-etch layer;

etching a via hole from the other face of the substrate;

depositing a coating of titanium-gold on the surface of the via hole;

locating the via hole from the first or epitaxial side of the device by electron beam techniques;

depositing a silicon nitride layer and a photoresist layer on the active layer;

patterning the silicon nitride and photoresist layers to define a two-element gate;

forming two gate elements of titanium-tungsten on the active layer in approximate alignment with the via hole;

removing the titanium coating on the surface of the via hole;

forming a patterned photoresist layer over the active layer to define a source window between the gate elements and two drain windows;

implanting silicon ions through the windows in the photoresist layer to form a source contact region in the active layer, in an area located between the gate elements and drain contact regions in the active layer;

forming another patterned photoresist layer over the active layer to define a source window only;

implanting sulfur ions to form an n+ source region in the stop-etch layer and between the gate elements;

annealing the structure after the foregoing implanting step, to diffuse some of the sulfur ions laterally in the stop-etch layer, to form an extended source region in partial overlapping relationship with the gate elements;

etching an opening in the source region, extending through to the metallized via hole;

depositing ohmic gold-germanium metal in the source region opening to establish good contact with the via hole metallization; and

forming metal drain contacts over the drain contact regions.