Power chip package

• US 4,538,170 A
• Filed: 01/03/1983
• Issued: 08/27/1985
• Est. Priority Date: 01/03/1983
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: General Electric Company
• Inventors: Yerman, Alexander J.
• Primary Examiner(s): Edlow, Martin H.
• Assistant Examiner(s): JACKSON JR, JEROME
• Application Number:
  US06/455,186
• Time in Patent Office: 967 Days
• Field of Search: 357/80, 357/81, 357/74, 357/68, 174/16 HS
• US Class Current: 257/705
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A heat-generating power semiconductor chip is mounted in a package to permit testing or use of the chip before or after mounting of the package to a heat spreader plate. A plurality of sheet metal leads are attached to a dielectric substrate, such as beryllia. The leads are patterned in mirror image fashion to a plurality of terminals on one side of the power chip. In one form, a further sheet metal lead is attached to a further dielectric substrate and is adapted to abut a terminal on the other side of the power chip. In another form, heat transfer structure is provided for transferring heat between the pair of dielectric substrates, thereby enabling heat to be removed from both sides of the power chip.

Claims

1. A power chip package comprising:

a power chip having a first terminal on one side thereof and a second terminal on the opposite side thereof;

a first dielectric substrate;

a first sheet metal lead attached to one side of said first dielectric substrate and patterned in mirror image fashion to, and attached to, said first terminal;

a second dielectric substrate;

a second sheet metal lead attached to one side of said second dielectric substrate and patterned in mirror image fashion to, and attached to, said second terminal; and

a heat transfer means in heat flow communication with said first and second dielectric substrates for transferring heat between said first and second dielectric substrates, said heat transfer means comprising a plurality of compacted folds of sheet metal interposed between said first and second dielectric substrates.

2. The power chip package of claim 1 wherein said first and second dielectric substrates are each selected from the group consisting of alumina and beryllia.

3. The power chip package of claim 1 wherein said first and second dielectric substrates each comprise beryllia.

4. The power chip package of claim 1 wherein said first and second sheet metal leads each comprise copper.

5. The power chip package of claim 1 further comprising:

a first eutectic composition situated between and integrally bonding together said first sheet metal lead and said first dielectric substrate; and

a second eutectic composition situated between and integrally bonding together said second sheet metal lead and said second substrate.

6. The power chip package of claim 1 further comprising a solderable metal layer attached to a further side of said first dielectric substrate.

7. The power chip package of claim 1 further comprising a solderable metal layer attached to a further side of said second dielectric substrate.

8. The power chip package of claim 1 wherein said power chip has a third terminal, said third terminal being formed on said one side of said power chip, and further comprising a third sheet metal lead attached to said one side of said first dielectric substrate and patterned in mirror image fashion to, and attached to, said third terminal.

9. The power chip package of claim 8 wherein:

said first and second dielectric substrates are each selected from the group consisting of alumina and beryllia; and

said first, second and third sheet metal leads each comprises copper.

10. The power chip package of claim 9 further comprising:

a first eutectic composition situated between and integrally bonding together said first sheet metal lead and said first dielectric substrate;

a second eutectic composition situated between and integrally bonding together said second sheet metal lead and said second dielectric substrate; and

a third eutectic composition situated between and integrally bonding together said third sheet metal lead and said first dielectric substrate.

11. The power chip package of claim 1 wherein said compacted folds of sheet metal interposed between said first and second dielectric substrates comprise leads of the power chip package.

13. The power chip package of claim 11 further comprising:

a plurality of eutectic compositions respectively situated between and integrally bonding together each of said plurality of sheet metal leads and said first dielectric substrate; and

a further eutectic composition situated between an integrally bonding together said further sheet metal lead and said second dielectric substrate.

14. The power chip package of claim 13 wherein said first and second dielectric substrates each comprise one of the group consisting of alumina and beryllia.

12. A package for a power chip comprising:

a first dielectric substrate;

a plurality of sheet metal leads attached to one side of said first dielectric substrate and patterned in mirror image fashion to the terminal pattern on one side of a power chip;

a second dielectric substrate;

a further sheet metal lead attached to one side of said second dielectric substrate and patterned in mirror image fashion to a terminal on another side of the power chip; and

heat transfer means for transferring heat between said first and second dielectric substrates, said heat transfer means comprising a plurality of compacted folds of sheet metal interposed between said first and second dielectric substrates.

15. The power chip package of claim 12 wherein said compacted folds of sheet metal interposed between said first and second dielectric substrates comprise leads of the power chip package.