Multiplex bus system for controlling the transmission of data between a master control unit and a plurality of remotely located receiver-transmitter units
First Claim
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1. A multiplex bus system comprising in combination:
- a master control unit (MCU) including a signal producing first clock source;
at least one receiver-transmit unit (RTU) including a signal producing second clock source;
bus means connecting said MCU and said at least one RTU for facilitating the transmission of information-bearing signals therebetween;
wherein said MCU transmits signals via said bus means to said RTU in the form of messages, each message comprising a synchronization pulse of known duration XT and a plurality of data bits of known duration T, wherein each of said messages includes a portion for the transmission of data bits from said RTU to said MCU;
said MCU including means utilizing said first clock source signal for determining said duration T;
said RTU including means responsive to the duration of said synchronization signal and to said second clock source signal for producing a signal representing said duration T as a function of said second clock source frequency; and
said RTU including means utilizing said signal representing said duration T for thereafter clocking said data bits from said MCU to said RTU into said RTU.
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Abstract
A multiplex bus system comprises a master control unit (MCU) connected to at least one receiver-transmit unit (RTU) by a data bus. The MCU transmits to the RTU a message comprising a synchronization pulse of known duration and successive time spaced timing signals separated by time duration T marking the boundaries of data bits to be transmitted from the RTU to the MCU. The RTU includes a clock pulse source which utilizes the synchronization pulse to determine the frequency of the clock pulse source in P pulses per duration T. The value P is used in conjunction with the timing signals to create properly timed data determining signals in the data bits.
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Citations
17 Claims
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1. A multiplex bus system comprising in combination:
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a master control unit (MCU) including a signal producing first clock source; at least one receiver-transmit unit (RTU) including a signal producing second clock source; bus means connecting said MCU and said at least one RTU for facilitating the transmission of information-bearing signals therebetween; wherein said MCU transmits signals via said bus means to said RTU in the form of messages, each message comprising a synchronization pulse of known duration XT and a plurality of data bits of known duration T, wherein each of said messages includes a portion for the transmission of data bits from said RTU to said MCU; said MCU including means utilizing said first clock source signal for determining said duration T; said RTU including means responsive to the duration of said synchronization signal and to said second clock source signal for producing a signal representing said duration T as a function of said second clock source frequency; and said RTU including means utilizing said signal representing said duration T for thereafter clocking said data bits from said MCU to said RTU into said RTU. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A multiplex bus system for interfacing between controlled devices and controlling devices in a vehicle comprising in combination:
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a master control unit (MCU) including a signal producing first clock source; a plurality of receiver-transmit units (RTU'"'"'s) each connected to one or more control devices for selectively passing operating power thereto and/or to one or more controlling devices for receiving signals therefrom corresponding to an action to be taken by an associated controlled device in response to a signal from a controlling device, said RTU including a second signal producing clock source; a bus means connected between said MCU and said RTU'"'"'s for facilitating the transfer of information-bearing signals therebetween; wherein said MCU transmits signals via said bus means seriatim to said RTU'"'"'s in the form of messages, each message comprising a synchronization pulse of known duration XT, a plurality of address bits and a plurality of data bits of duration T, said MCU including means utilizing said first clock source signal for setting said durations XT and T; each said RTU including means responsive to the duration of said synchronization pulse and to said second clock source signal for producing an RTU timing signal representing time duration T as a function of said second clock source frequency. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification