Multiplex bus system for controlling the transmission of data between a master control unit and a plurality of remotely located receiver-transmitter units

• US 4,538,262 A
• Filed: 08/03/1983
• Issued: 08/27/1985
• Est. Priority Date: 08/03/1983
• Status: Expired due to Fees

• Current Assignee: RCA Corporation
• Original Assignee: RCA Corporation
• Inventors: Sinniger, Joseph O., Peterson, Richard M.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Kuntz, Curtis A.
• Application Number:
  US06/520,122
• Time in Patent Office: 755 Days
• Field of Search: 370/100, 370/85, 307/10 R
• US Class Current: 370/431
• CPC Class Codes: B60R 16/0315 using multiplexing techniques multiplexing for transmission of signals G08C15/00; multiplexing for electrical communication in general H04J
• CPC Class Codes: H04L 12/40 Bus networks
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 2012/40273 the transportation system being a vehicle
• CPC Class Codes: H04L 7/06 the synchronisation signals differing from the information signals in amplitude, polarity or frequency or length
• CPC Class Codes: H04Q 9/14 Calling by using pulses

Abstract

A multiplex bus system comprises a master control unit (MCU) connected to at least one receiver-transmit unit (RTU) by a data bus. The MCU transmits to the RTU a message comprising a synchronization pulse of known duration and successive time spaced timing signals separated by time duration T marking the boundaries of data bits to be transmitted from the RTU to the MCU. The RTU includes a clock pulse source which utilizes the synchronization pulse to determine the frequency of the clock pulse source in P pulses per duration T. The value P is used in conjunction with the timing signals to create properly timed data determining signals in the data bits.

Claims

1. A multiplex bus system comprising in combination:

a master control unit (MCU) including a signal producing first clock source;

at least one receiver-transmit unit (RTU) including a signal producing second clock source;

bus means connecting said MCU and said at least one RTU for facilitating the transmission of information-bearing signals therebetween;

wherein said MCU transmits signals via said bus means to said RTU in the form of messages, each message comprising a synchronization pulse of known duration XT and a plurality of data bits of known duration T, wherein each of said messages includes a portion for the transmission of data bits from said RTU to said MCU;

said MCU including means utilizing said first clock source signal for determining said duration T;

said RTU including means responsive to the duration of said synchronization signal and to said second clock source signal for producing a signal representing said duration T as a function of said second clock source frequency; and

said RTU including means utilizing said signal representing said duration T for thereafter clocking said data bits from said MCU to said RTU into said RTU.

2. The combination as set forth in claim 1 wherein said MCU includes means for generating a signal representing said data bits and wherein the signal for each data bit comprises first and second transitions from a first voltage level to a second voltage level and spaced time duration T apart and wherein the second transition of one data bit is the first transition of a next successive data bit and wherein said signal representing each data bit transmitted from said MCU to said RTU comprises a third transition from said second voltage level to said first voltage level and occurring intermediate said first and second transitions and nearer in time to the occurrence of said first or second transition depending on whether the data bit has a One or Zero value, said data bits representing signal including, for each data bit, a second voltage level portion existing from the occurrence of said first transition to the occurrence of said third transition and a first voltage level portion existing from the occurrence of said third transition to the occurrence of said second transition.

3. The combination as set forth in claim 2 wherein for said data bits to be transmitted from said RTU to said MCU during the transmission of said message, said RTU includes means for generating a signal for each data bit comprising said third transition, said third transition occurring nearer in time to the occurrence of said first or second transition depending on whether the data bit has a One or Zero value, said signal also including a second voltage level portion existing from a first given time following the occurrence of said first transition until the occurrence of said third transition and a first voltage level portion existing from the occurrence of said third transition until a second given time less than the time of occurrence of said second transition, said first and second given times being a function of time T and of the frequency of said RTU clock, said signal from said MCU for data bits being transmitted from said RTU to MCU including said second voltage level signal existing from said first transition until a third given time which is at least equal to said first given time and including said first voltage level portion existing from a fourth given time no greater than said second given time from the occurrence of said second transition towards said third transition, said third and fourth times being a function of the frequency of said MCU clock.

4. The combination as set forth in claim 1 wherein said means for producing a signal representing said duration T comprises counter means responsive to the synchronization portion of said message and to said second clock source signal for counting second clock cycles during the presence of said synchronization portion and means for scaling by X the count so obtained, the scaled number corresponding to the number of clock pulse cycles in time duration T.

5. The combination as set forth in claim 3 wherein said means for producing a signal representing said duration T comprises counter means responsive to the synchronization portion of said message and to said second clock source signal for counting second clock cycles during the presence of said synchronization portion and means for scaling by X the count so obtained, the scaled number corresponding to the number of clock pulse cycles in time duration T.

6. The combination as set forth in claim 4 wherein said means for producing a signal representing said duration T further includes means for further scaling said scaled number to obtain the number of RTU clock cycles in a time duration which is a fraction Y of T and timing means responsive to the fraction Y of T time number and to each said data bit first transition for producing timing pulses every T·

Y following each said data bit first transition.

7. The combination as set forth in claim 6 wherein said means for generating a signal for each data bit to be transmitted from said RTU to said MCU is responsive to said timing pulses at T·

Y for determining the timing of each said third transition relative to its associated first transition.

8. A multiplex bus system for interfacing between controlled devices and controlling devices in a vehicle comprising in combination:

a master control unit (MCU) including a signal producing first clock source;

a plurality of receiver-transmit units (RTU'"'"'s) each connected to one or more control devices for selectively passing operating power thereto and/or to one or more controlling devices for receiving signals therefrom corresponding to an action to be taken by an associated controlled device in response to a signal from a controlling device, said RTU including a second signal producing clock source;

a bus means connected between said MCU and said RTU'"'"'s for facilitating the transfer of information-bearing signals therebetween;

wherein said MCU transmits signals via said bus means seriatim to said RTU'"'"'s in the form of messages, each message comprising a synchronization pulse of known duration XT, a plurality of address bits and a plurality of data bits of duration T, said MCU including means utilizing said first clock source signal for setting said durations XT and T;

each said RTU including means responsive to the duration of said synchronization pulse and to said second clock source signal for producing an RTU timing signal representing time duration T as a function of said second clock source frequency.

9. The combination as set forth in claim 8 wherein each said RTU includes means for presetting a unique address therein and including means responsive to the address containing portion of said message and to said RTU timing signal for decoding into One and Zero values the address portion of said message and for comparing the decoded message address with the preset address and for producing a control signal if there is a equality.

10. The combination as set forth in claim 8 wherein a said RTU includes a data storage means coupled to at least one of said controlled devices and including means responsive to said control signal, to said message signal and to said RTU timing signal for clocking said data bits received from said MCU into said data storage means for controlling said controlled device or devices coupled thereto.

11. The combination as set forth in claim 9 wherein a said RTU includes a data storage means coupled to at least one of said controlled devices and including means responsive to said control signal, to said message signal and to said RTU timing signal for clocking said data bits received from said MCU into said data storage means for controlling said controlled device or devices coupled thereto.

12. The combination as set forth in claim 8 wherein said MCU includes means for generating a signal representing said data bits and wherein the signal for each data bit comprises first and second transitions from a first voltage level to a second voltage level and spaced T apart and wherein the second transition of one data bit is the first transition of a next successive data bit and wherein said signal representing each data bit transmitted from said MCU to said RTU comprises a third transition from said second voltage level to said first voltage level and positioned intermediate said first and second transitions and closer to said first or second transition depending on whether the data bit has a One or Zero value, said data bits representing signal including a second voltage level portion extending from said first transition to said third transition and a first voltage level portion extending from said third transition to said second transition.

13. The combination as set forth in claim 12 wherein for said data bits to be transmitted from a said RTU to said MCU during the transmission of said message, said RTU includes means for generating a signal for each data bit comprising said third transition, said third transition occurring nearer in time to the occurrence of said first or second transition depending on whether the associated controlling device causes the data bit to have a One or Zero value, said signal also including a second voltage level portion existing from a first given time following the occurrence of said first transition until the occurrence of said third transition and a first voltage level portion existing from the occurrence of said third transition until a second given time less than the time of occurrence of said second transition, said first and second given times being a function of time T and of the frequency of said RTU clock, said signal from said MCU for data bits being transmitted from a said RTU to MCU including said second voltage level signal existing from said first transition until a third given time which is at least equal to said first given time and including said first voltage level portion existing from a fourth given time no greater than said second given time from the occurrence of said second transition towards said third transition, said third and fourth times being a function of the frequency of said MCU clock.

14. The combination as set forth in claim 8 wherein said means for producing a signal determining said duration T comprises counter means responsive to the sync portion of said message and to said second clock signal for counting second clock cycles during the presence of said sync portion and means for scaling by X the count so obtained, the scaled number corresponding to the number of clock pulse cycles in time duration T.

15. The combination as set forth in claim 13 wherein said means for producing a signal determining said duration T comprises counter means responsive to the sync portion of said message and to said second clock signal for counting second clock cycles during the presence of said sync portion and means for scaling by X the count so obtained, the scaled number corresponding to the number of clock pulse cycles in time duration T.

16. The combination as set forth in claim 14 wherein said means for producing a signal determining said duration T further includes means for further scaling said scaled number to obtain the number of RTU clock cycles in a time duration which is a fraction Y of T and timing means responsive to the fraction Y of T time number and to each said data bit first transition for producing timing pulses every T÷

Y following each said data bit first transition.

17. The combination as set forth in claim 16 wherein said means for generating a signal for each data bit to be transmitted from said RTU to said MCU is responsive to said timing pulses at T÷

Y for determining the timing of each said third transition relative to its associated first transition.