Hybrid integrated circuit device

• US 4,539,622 A
• Filed: 10/25/1984
• Issued: 09/03/1985
• Est. Priority Date: 06/25/1981
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Akasaki, Hidehiko
• Primary Examiner(s): Kucia, R. R.
• Application Number:
  US06/664,931
• Time in Patent Office: 313 Days
• Field of Search: 174/52 S, 174/52 FP, 361/393, 361/395, 361/401, 361/402, 361/414
• US Class Current: 361/764
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 23/057 the leads being parallel to the base
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01046 Palladium [Pd]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 LASER
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 Multilayer substrate
• CPC Class Codes: H01L 2924/15312 being a pin array, e.g. PGA
• CPC Class Codes: H01L 2924/15787 Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]

Abstract

A hybrid integrated circuit device comprising in combination, a semiconductor integrated circuit element (1) and a film resistor pattern (7). The film resistor pattern is formed on the outer surface of a base (6) which is mounted on a multilayer ceramic package (2) which incorporates the element (1). In this assembled and operated hybrid device, function trimming of the film resistor pattern can be carried out by using a computer and testing is easier than is capable with prior art devices.

Claims

1. A hybrid integrated circuit device, comprising:

(a) a semiconductor circuit element;

(b) a multilayer ceramic package including--

(i) a first frame member having a first surface and a second surface and creating a cavity therebetween for incorporating said semiconductor circuit element therein,

(ii) a cap mounted on the second surface of said first frame member so as to seal said cavity, and

(iii) a second frame member having a first surface and a second surface, wherein the first surface of the second frame member is mounted on said second surface of said first frame member and surrounding said cap, said cap being thinner than said second frame member;

(c) external connection terminals mounted on the multilayer ceramic package opposite the second frame member;

(d) a base having a first surface and a second surface, wherein the base'"'"'s first surface is mounted on said second surface of said second frame member;

(e) first and second conductive patterns formed on said base;

said second conductive pattern being bonded to said first conductive pattern by soldering; and

(f) a film resistor pattern formed on the second surface of said base and electrically connected to said first and second conductive patterns and to said semiconductor circuit element, said film resistor pattern being trimmed so that the resistance value of said film resistor pattern is adapted to the characteristics of said semiconductor circuit element.

2. A device as set forth in claim 1, wherein said multilayer ceramic package is manufactured by coating the outer surface of or through holes of a plurality of raw ceramic sheets with a layer of molybdenum-manganese and then laminating the plurality of raw ceramic sheets, which are then fired in a reduction atmosphere.

3. A device as set forth in claim 1, wherein said film resistor pattern is manufactured by coating the second surface of said base with a mixture of oxide and glass powder and then firing it in an oxidation atmosphere.

4. A device as set forth in claim 3, wherein said oxide comprises ruthenium oxide.