Program patching in microcomputer

• US 4,542,453 A
• Filed: 02/19/1982
• Issued: 09/17/1985
• Est. Priority Date: 02/19/1982
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation, Texas Instruments, Inc.
• Original Assignee: International Business Machines Corporation, Texas Instruments, Inc.
• Inventors: Patrick, Michael J., Snider, David M.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Mills, John G.
• Application Number:
  US06/350,513
• Time in Patent Office: 1,306 Days
• Field of Search: 364/200, 364/900
• US Class Current: 714/6.13
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 8/66 of program code stored in read-only memory [ROM]
• CPC Class Codes: G06F 9/328 for runtime instruction patching

Abstract

A single-chip microcomputer device contains on-chip program storage in a read-only memory (ROM), and this program may be corrected or updated by patching. The ROM addresses are applied to an off-chip memory device containing one bit for each potential ROM address, and each bit is set to mark the beginning address of code to be patched; an interrupt is signalled when one of these set bits is accessed by an address occurring during operation of the microcomputer. The interrupt causes the processor to branch to an off-chip program memory to insert the patch code. The patch ends in a branch back to the on-chip ROM.

Claims

1. A data processing system comprising:

(a) a processor containing an arithmetic logic unit, a program store memory with addressing means, data storage means, and control means including an instruction register receiving instruction words from the program store to generate commands for defining the operations of the processor;

(b) peripheral input/output circuitry for coupling data between the processor and the peripheral equipment;

(c) bus means connecting terminals of the processor to the peripheral input/output circuitry; and

(d) program patching means coupled to said bus means, which enables online updating of processor program instructions without modifying the program store, comprising;

a patch memory for storage of instruction words, addressing means for the patch memory coupled to said addressing means for the program store via said bus means,

output means for the patch memory coupled via said bus means to the control means in the processor for delivery of instruction words to said control means,

and patch control means including a patch control memory connected via said bus means to said addressing means for the program store, and addressed simultaneously with the program store memory, and responsive to each address applied to the program store, and producing a control signal to said processor in response to a marker bit being detected in said patch control memory, said control signal being applied to said processor to interrupt a sequence of addresses applied by said addressing means to the program store when an address requiring a patch is detected, said processor generating a new address for the patch code when said interrupt occurs.

2. A system according to claim 1 wherein the processor is a microcomputer device constructed as a single semiconductor integrated circuit.

3. A system according to claim 1 wherein said patch memory is a programmable read-only memory.

4. A system according to claim wherein said patch control means includes a patch control memory device containing one bit for each addressable location in the program store.

5. A system according to claim 4 wherein the processor includes interrupt means coupled to a one-bit output of the patch control memory device to receive said control signal, and functioning by interrupting said sequence of addresses to interrupt execution in the processor of a sequence of said instruction words in order to interpose a patch of a different sequence of instruction words fetched from said patch memory based upon said new address.

6. A microcomputer system comprising:

a processor device containing a permanently-programmed read-only memory, a program counter, instruction-execution means including an instruction register, and interrupt means, all in a single semiconductor device;

an auxiliary program memory having an address input and having an output;

address/data bus means for transferring all of the addresses from the program counter of the processor device to the address input of the auxiliary program memory and for transferring instructions from the output of the auxiliary program memory to the instruction register;

tag bit storage means also responsive to all of the addresses from the program counter applied to said address input to produce an output bit for each such address;

the interrupt means of the processor device receiving said output bit from the tag bit storage means and controlling loading of the instruction register either from said read-only memory or from the address/data bus means.

7. A system according to claim 6 wherein the tag bit storage means is in a one-bit wide memory device physically separate from the auxiliary program memory, and the address range of the auxiliary program memory is much less than that of the read-only memory.

8. A system according to claim 7 wherein the auxiliary program memory contains a plurality of patch code instruction sequences and a look-up table of the addresses of the sequences.

9. A system according to claim 6 whererin the tag bit memory is in the same memory device as the auxiliary program memory, and the auxiliary program memory has an address range equal to that of the read-only memory.

10. A method of patching instruction code in a permanently programmed read only memory, while leaving the code in said read only memory in tact, coomprising the steps of:

applying a sequence of addresses to said read only memory and also applying each address of said sequence of addresses to a separate one bit wide memory device, containing a marker bit for each of said sequence of addresses;

coupling an interrupt output on the one bit wide memory device to instruction processing means to cause an interruption in said sequence of addresses when the addressed marker bit in said memory device produced at said output is set at a given logic level;

and if such interruption occurs then applying addresses to said auxiliary memory separate from said read only memory containing patch code, such addresses being outside the range of said sequence of addresses.

11. A method according to claim 10 wherein the one-bit wide memory device is programmed to contain 1 and 0 logic levels depending upon the address locations to be patched.

12. A method according to claim 10 including the step of programming the auxiliary memory to contain a plurality of patch code sequences at different starting addresses in the auxiliary memory.

13. A method according to claim 12 wherein the auxiliary memory contains a look-up table of said different starting addresses.

14. A method according to claim 13 including the step of selecting a starting address from the look-up table based on the address in said sequence which produced said output.