Semiconductor integrated circuit

• US 4,542,485 A
• Filed: 01/08/1982
• Issued: 09/17/1985
• Est. Priority Date: 01/14/1981
• Status: Expired due to Term

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Asano, Masamichi, Iwahashi, Hiroshi
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/337,969
• Time in Patent Office: 1,348 Days
• Field of Search: 365/189, 365/182, 365/230
• US Class Current: 365/189.09
• CPC Class Codes: G05F 3/242 with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
• CPC Class Codes: G11C 17/08 using semiconductor devices, e.g. bipolar elements G11C17/06, G11C17/14 take precedence
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/00 Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A semiconductor integrated circuit comprises a first MOS transistor connected at the drain to a power source terminal of a high potential power source and supplied at the gate with a predetermined voltage, a logic circuit including MOS transistors provided between the power source terminal and a circuit point at a potential and operating in a potential range between the high potential and the circuit point, and a circuit for making the potential at the circuit point coincide with the potential at the source of the first MOS transistor.

Claims

1. A semiconductor integrated circuit device comprising:

a high potential power source;

a low potential power source;

a circuit for applying an intermediate potential between high and low potentials of said power sources to a circuit point, said intermediate potential applying circuit including a first MOS transistor connected at one end of its drain-source path to said high potential power source and having a predetermined voltage signal at its gate, a first differential amplifier circuit for receiving at one of the input terminals a voltage signal at the other end of said first MOS drain-source path and at another input terminal a voltage signal at said circuit point, a second differential amplifier for receiving at one of the input terminals a first output signal of said first differential amplifier circuit, and an MOS transistor connected between said circuit point and said low potential power source and receiving at its gate the output signal from said second amplifier circuit; and

a logic circuit connected to said high potential power source and said circuit point and operating in a voltage range betweeh the potentials of said high potential power source and at said circuit point.

2. A semiconductor integrated circuit device according to claim 27, wherein said intermediate potential applying circuit includes a first MOS transistor connected at one end of its drain-source path to said high potential power source and having a predetermined voltage signal at its gate, a first differential amplifier circuit for receiving at one of the input terminals a voltage signal at the other end of said first MOS transistor drain-source path and at another input terminal a voltage signal at said circuit point, a second differential amplifier for receiving at one of the input terminals a first output signal of said first differential amplifier circuit, and at another input terminal a second output signal from said first differential amplifier circuit, and an MOS transistor connected between said circuit point and said low potential power source and coupled at the gate with the output signal from said second amplifier circuit.

3. A semiconductor integrated circuit device according to claim 27, wherein said intermediate potential applying circuit includes a first MOS transistor connected at one end of its drain-source path to said high potential power source and having its gate connected to a predetermined voltage, a differential amplifier circuit connected at one of the input terminals to a voltage signal at the other end of the drain-source path of said first MOS transistor and at another input terminal a voltage at said circuit point, an intermediate amplifier circuit for receiving an output signal from said differential amplifier circuit, and an MOS transistor for receiving at the gate an output signal from said intermediate amplifier circuit, of which the drain-source path is connected between said circuit point and said low potential power source.

4. A semiconductor memory device comprising

a plurality of column lines;

a plurality of row lines crossing said column lines;

memory cells each including an MOS transistor disposed at cross points of said column lines and said row lines, the drain of each MOS transistor being connected to a corresponding column line; and

means connected between a high potential power source and a low potential power source for applying a signal at a given potential between high and low potentials of said power source to the source of said MOS transistor constituting each memory cell, said signal applying means comprising a transistor circuit including a transistor equivalent to said MOS transistor constituting said memory cell, means for applying a signal, which is at a potential substantially equal to the potential on a non-selected row line, to the gate of said equivalent MOS transistor, and means for fetching an output signal from said equivalent transistor and supplying the output signal to the source-drain path of the MOS transistors in said memory cells.

5. A semiconductor integrated circuit device comprising:

a control MOS transistor of the depletion type gate-controlled by a first input signal;

a drive MOS transistor supplied with a power source voltage through said control MOS transistor and gatecontrolled by a second input signal; and

means for connecting the drain and gate of said drive MOS transistor in a power down mode.

6. A semiconductor integrated circuit device according to claim 5, wherein a load circuit is provided between said control MOS transistor and said drive MOS transistor.

7. A semiconductor integrated circuit according to claim 6, wherein said load circuit is a depletion type MOS transistor and an absolute value of a threshold voltage of each of said depletion type MOS transistors is higher than an absolute value of a threshold voltage of each of said control MOS transistors.

8. A semiconductor integrated circuit device comprising:

a circuit including a plurality of MOS transistor circuits, including at least a prestage and a post-stage, each said circuit being made up of a control MOS transistor of the depletion type gate-controlled by a first input signal and drive MOS transistor supplied with a power source voltage through said control MOS transistor;

a connection line for connecting the drain of said drive MOS transistor of the prestage with the gate of said drive MOS transistor of the post-stage;

first means for interconnecting the drain and the gate of said drive MOS transistor of the respective stages except the prestage; and

second means for shutting off the source current of said drive MOS transistor of the first stage in a power down mode.

9. A semiconductor integrated circuit device according to claim 8, wherein a load circuit is provided between said control MOS transistor and said drive MOS transistor.

10. A semiconductor integrated circuit according to claim 9, wherein said load circuit is a depletion type MOS transistor, and an absolute value of a threshold voltage of each of said depletion type MOS transistors is higher than an absolute value of a threshold voltage of each of said control MOS transistors.

11. A decoder circuit comprising:

a main decoder including a plurality of first MOS transistors connected in parallel one another for receiving at the gates a selection signal, a first MOS transistor for receiving at the gate a first input signal connected between a high potential power source and one end of the drain-source path of each of said first MOS transistor, a plurality of second MOS transistors connected between said one ends of said first MOS transistors and word lines corresponding to said one ends, a plurality of third MOS transistors of which drain-source paths are respectively connected at one ends to the word line said terminals of said second MOS transistors, and a second control MOS transistor of which the drain-source path is connected at one end to said one ends of the drain-source paths of said first MOS transistors, and receives at the gate a second input signal out of phase with respect to said first input signal; and

means connected to the other end of said second control MOS transistor in said main decoder, and for supplying a potential of the gate potential of said first control MOS transistor or more to the source of said first control MOS transistor in a power down mode.

12. A semiconductor memory device comprising:

a plurality of column lines;

a plurality of row lines crossing said column lines;

memory cells each including an MOS transistor disposed at cross points of said column lines and said row lines, the drain of each said MOS transistor being connected to a corresponding column line; and

means connected between a high potential power source and a low potential power source for applying a signal at a given potential between high and low potentials of said power sources to the source of said MOS transistor constituting each memory cell, said signal applying means comprising an MOS transistor which is connected at one end of the drain-source path to ground and at the other end to one end of the drain-source path of the MOS transistors of said memory cells.

13. A semiconductor integrated circuit device comprising:

a high potential power source;

a low potential power source;

a circuit for applying an intermediate potential between said high and low potentials to a circuit point, said intermediate potential applying circuit including a first MOS transistor having a drain-source path connected at one end of said high potential power source and having a gate connected to a predetermined voltage, a differential amplifier circuit connected at one of the input terminals to a voltage signal at the other end of the drain-source path of said first MOS transistor and at another input terminal to a voltage at said circuit point, an intermediate amplifier circuit for receiving an output signal from said differential amplifier circuit, and an MOS transistor having a gate receiving an output signal from said intermediate amplifier circuit, and having a drain-source path being connected between said circuit point and said low potential power source; and

a logic circuit connected to said high potential power source and said circuit point and operating in a voltage range between the potentials of said high potential power source and at said circuit point.