Memory identification apparatus and method

• US 4,545,010 A
• Filed: 03/31/1983
• Issued: 10/01/1985
• Est. Priority Date: 03/31/1983
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Johnson, Robert B., Nibby, Chester M. Jr., Salas, Edward R., Fisher, Edwin P., Boudreau, Daniel A.
• Primary Examiner(s): Zache, Raulfe B.
• Application Number:
  US06/480,964
• Time in Patent Office: 915 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0653 with centralised address assignment

Abstract

A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and an identification section containing circuits for generating signals indicating the board density and the type of memory parts used in constructing the board'"'"'s memory section. The main board control circuits include a number of decoder circuits which couple to the identification and to the memory section of each memory module board. The decoder circuits receive different address bit combinations of a predetermined multibit address portion of each memory request address. In response to signals generated by the identification sections of the installed memory boards, the decoder circuits are selectively enabled to decode those bit combinations of the address portion specified by the sections for enabling successive addressing of all of the blocks of location within the system.

Claims

1. A memory system comprising a number of memory module boards and a main board coupled to said number of module boards, said main board including decoder circuit means for generating a number of decode selection signals in response to a predetermined multibit address portion of an address of each memory request applied to said system, said address being for specifying a location within said system to be accessed, each of said memory module boards including:

a memory section coupled to said decode circuit means for receiving selected ones of said decode selection signals, said memory section having a number of blocks of addressable memory chips, each block including a plurality of storage locations; and

an identification section coupled to said decoder circuit means, said identification section including means for supplying a plurality of identification signals coded for indicating the type of chips and the populated density of said board,

said decoder circuit means being conditioned by said identification signals for decoding different address bit combinations of said predetermined multibit address portion selected as a function of said coded identification signals to generate said number of said decode selection signals in a manner which enables successive addressing of said pluralities of storage locations within each of said blocks of said number of memory module boards.

2. The system of claim 1 wherein said predetermined multibit address portion corresponds to a number of most significant address bits coded for specfying a maximum number of blocks of memory chips includable on said number of memory boards installable within said memory system, said memory module boards being identical and said identification section of each board being connected in common.

3. The system of claim 1 wherein said decoder circuit means includes a plurality of decoder circuits, each of said plurality of said decoder circuits having an enabling input circuit and an input select circuit, said enabling input circuit of each of said plurality of said decoder circuits being coupled to receive at least one of said coded identification signals and said input select circuit of each decoder circuit being coupled to receive at least one of said different address bit combinations of said predetermined multibit address portion, each decoder circuit when enabled by said coded identification signals being operative to generate said decode selection signals for application to said memory module boards in said predetermined sequence as specified by the coding of said different address bit combination applied to said decoder circuit input select circuit.

4. The system of claim 3 wherein said memory request address further includes row and column address portions, said main board further including an address section comprising:

a plurality of address registers, a first one of said registers being coupled to said decoder circuit means and connected for storing said predetermined multibit address, second and third ones of said registers being coupled to said memory module boards and connected for storing said row and column address portions respectively; and

a multiplexer circuit having a number of input control terminals, a plurality of input terminals and at least one output terminal, said input control terminals being connected to receive said second one of said identification signals and a timing signal coded for indicating the portion of a memory cycle of operation being performed, each of said plurality of input terminals being connected to said first address register for receiving a different predetermined one of said address bits of said predetermined multibit address portion and said number of output terminals being coupled to said memory module boards, said multiplexer circuit being enabled for operation when said second one of said identification signals is coded to specify said first type of chip, and said multiplexer circuit when enabled for operation being conditioned to apply to said output terminal, said different predetermined ones of said address bits during said portion of said memory cycle specified by the coding of said timing signal as the most significant address bits of said row and column address portions applied to said memory module boards by said first and second address registers.

5. The system of claim 4 wherein said main board further includes timing and control circuits, coupled to said address register section and to said memory module boards, said circuits being operative to generate a sequence of timing signals for conditioning said memory module boards for performing a memory cycle of operation in response to said each memory request, a first one of said timing signals being generated at the start of said memory cycle of operation for strobing said row address portion into said memory chips of one of said number of rows of said memory module boards selected by said decoder circuit means and a second one of said timing signals corresponding to said timing signal, said second timing signal being generated subsequent to said start of said memory cycle of operation for conditioning said third address register to apply said column address portion to said memory module boards.

6. The memory system of claim 5 wherein said memory section of each memory board further includes:

a number of jumper conductor means selectively connected to said multiplexer circuit output terminal for receiving said most significant row and column address bits, said number of jumper conductor means being connected to said multiplexer circuit when a first one of said identification signals is coded to specify that said memory section contains said first type of chips and said number of jumper conductor means being disconnected from said multiplexer circuit when said first one of said identification signals is coded to specify that said memory section contains a second type of memory chips.

7. The memory system of claim 5 wherein said memory section of each memory module board further includes:

a plurality of gating circuits corresponding in number to the maximum number of blocks includable in said section, each of said gating circuits having a plurality of input terminals and an output terminal, one of said plurality of input terminals being connected to said timing and control circuits for receiving said first one of said timing signals, another one of said plurality of input terminals being connected to said plurality of decoder circuits for receiving a corresponding one of said row decode selection signals and said output terminal being connected to each of said chips of a corresponding one of said blocks, each of said gating circuits being operative in response to said first one of said timing signals and said decode selection signals to generate an enable output signal for simultaneously conditioning each of said chips of said corresponding one of said blocks to store said row address portion.

8. The system of claim 1 wherein said memory module boards are constructed to have one of a plurality of densities and to have one of a plurality of types of memory chips, said means of said identification section including a plurality of output terminals and a corresponding number of configurable jumper conductor means selectively connected to different ones of said output terminals for generating said coded identification signals.

9. The system of claim 8 wherein a first one of said number of configurable jumper conductor means when connected to a first one of said output terminals generates a first one of said identification signals coded to specify that said memory section contains first types of memory chips in said number of blocks and said first one of said number of configurable jumper conductor means when disconnected from said first one of said output terminals generates said first one of said identification signals coded to specify that said memory section contains second types of memory chips in said number of blocks.

10. The system of claim 9 wherein a second one of said number of configurable jumper connector means when connected to a second one of said output terminals generates a second one of said identification signals coded to specify that said memory module board has a first density of said blocks of memory chips and said second one of said number of configurable jumper conductor means when disconnected from said second one of said output terminals generates said second one of said identification signals coded to specify that said memory module board contains a second density of said rows of memory chips.

11. The system of claim 10 wherein said decoder circuit means includes means for connecting in common said first and second ones of said output terminals of said identification sections of memory module boards.

12. The system of claim 11 wherein said decoder circuit means further includes:

a first decoder circuit having at least one enabling input terminal, a plurality of input select terminals, and a plurality of output terminals, said enabling input terminal being connected to receive said first and second ones of said identification signals and said plurality of input select terminals being connected to receive a first combination of address bits of said multibit address portion, said first decoder circuit being enabled for operation only when said first and second ones of said identification signals are coded to specify that said memory sections of said number of memory module boards have said second density and contain said second type of memory chips and said first decoder circuit when enabled being operative to generate a first group of said number of said row decode selection signals in said predetermined sequence for successively addressing blocks of storage locations within each of said number of memory module boards.

13. The system of claim 12 wherein said number of memory module boards is two, said second type of chip is a 64K RAM chip and said second density is normal density, each of said number of blocks of a first of said two boards being coupled to a different one of a first group of said first decoder circuit output terminals and each of said number of blocks of a second of said two boards being coupled to a different one of a second group of said first decoder circuit output terminals, said first decoder circuit being operative in response to successively increasing values of said first combination of address bits to enable for access locations in successive blocks of 64K RAM chips in said first and then said second memory module boards.

14. The system of claim 13 wherein each of said memory sections of said first and second boards is partially populated with blocks of chips corresponding to said normal density.

15. The system of claim 12 wherein said decoder circuit means further includes:

a second decoder circuit having a number of enabling input terminals, a plurality of input select terminals and a plurality of output terminals, said number of enabling input terminals being connected to receive said first and second ones of said identification signals and said plurality of input select terminals being connected to receive a second combination of address bits of said multibit address portion, said second decoder circuit being enabled for operation only when said first and second ones of said identification signals are coded to specify that said memory sections of said number of memory module boards have said first density and contain said second type of memory chips and said second decoder circuit when enabled being operative to generate said number of said decode selection signals in said predetermined sequence for successively addressing blocks of storage locations within each of said number of memory module boards.

16. The system of claim 15 wherein said number of memory module boards is at least two, said second type of chip is a 64K RAM chip and said first density is double density, each of said number of said blocks of said two boards being coupled to different ones of said second decoder circuit output terminals, said second decoder circuit being operative in response to successively increasing values of said second combination of address bits to enable for access storage locations in successive groups of blocks of 64K RAM chips in said first and second memory module boards.

17. The system of claim 16 wherein said memory sections of said boards are fully populated with blocks of chips corresponding to said double density.

18. The system of claim 15 wherein said decoder circuit means further includes:

a third decoder circuit having at least one enabling input terminal, a plurality of input select terminals and a plurality of output terminals, said enabling input terminal being connected to receive said second one of said identification signals and said plurality of input select terminals being connected to receive a third combination of address bits of said multibit address portion, said third decoder circuit being enabled for operation only when said second one of said identification signals is coded to specify that said memory sections of said number of memory module boards contain said first type of memory chips and said third decoder circuit when enabled being operative to generate a portion of said number of said decode selection signals in said predetermined sequence for successively addressing blocks of storage locations within each of said number of memory module boards.

19. The system of claim 15 wherein said number of memory module boards is one and said first type of chip is a 256K RAM chip, each of said number of rows of said board being coupled to a different one of said third decoder circuit output terminals, said third decoder circuit being operative in response to successively increasing values of said third combination of address bits to enable for access storage locations in successive blocks of 256K RAM chips in said memory module board.

20. The system of claim 19 wherein said memory section of said board is fully populated with blocks of chips corresponding to said double density.

21. The system of claim 18 wherein said enabling input terminal of said third decoder circuit is connected to receive said first one of said identification signals, said third decoder being enabled for operation only when said first and second ones of said identification signals are coded to specify that said memory sections of said number of memory module boards have said second density and contain said first type of memory chips, and said third decoder circuit when enabled for operation being operative to generate said portion of said number of said row decode selection signals in said predetermined sequence for successively addressing blocks of storage locations within each of said number of memory module boards.

22. The system of claim 21 wherein said number of said memory module boards is at least two, said first type of chip is a 256K RAM chip and said second density is normal density, each of said number of blocks of a first of said two boards being coupled to a different one of a first group of said third decoder circuit output terminals and each of said number of blocks of a second of said two boards being coupled to a different one of a second group of said third decoder circuit output terminals, said third decoder circuit being operative in response to successively increasing values of said third combination of address bits to enable for access locations in successive blocks of 256K RAM chips in said first and then in said second memory module boards.

23. The system of claim 22 wherein each of said memory sections of said boards is partially populated with blocks of chips corresponding to said normal density.

24. The system of claim 18 wherein said decoder circuit means further includes:

a fourth decoder circuit having a number of enabling input terminals, a plurality of input select terminals and a plurality of output terminals, said enabling input terminals being connected to receive said first and second ones of said identification signals and said plurality of input select terminals being connected to receive a fourth combination of address bits of said multibit address portion increased to provide an expanded addressing capability, said fourth decoder circuit being enabled for operation only when said first and second ones of said identification signals are coded to specify that said number of memory module boards have said first density and contain said first type of memory chips and said fourth decoder circuit when enabled for operation being operative to generate said number of said decode selection signals in said predetermined sequence for successively addressing blocks of storage locations within each of said number of memory module boards.

25. The system of claim 24 wherein said number of said memory module boards is at least two, said first type of chip is a 256K RAM chip and said first density is double density, each of said blocks of said two boards being coupled to a different one of said fourth decoder circuit output terminals, said fourth decoder circuit being operative in response to successively increasing values of said fourth combination of address bits to enable for access, storage locations in successive groups of blocks of 256K RAM chips in said first and second memory module boards.

26. The system of claim 25 wherein said memory sections of said boards are fully populated with blocks of chips corresponding to said double density.

27. The system of claim 11 wherein said decoder circuit means further comprises a number of decoder circuits including a first decoder circuit having at least one enabling input terminal, a plurality of input select terminals and a plurality of output terminals, said one enabling input terminal being connected to receive said first one of said identification signals and said input select terminals being selectively connected to receive first and second combinations of address bits of said multibit address portion, said first decoder circuit being enabled for operation when said first one of said identification signals is coded to specify said second density and said first decoder circuit when enabled being operative to generate a first group of said number of said row decode selection signals in said predetermined sequence for addressing storage locations within successive blocks of first or second types of memory chips in each of said number of memory module boards.

28. The system of claim 27 wherein said number of memory module boards is at least two, said first or second type is a 256K RAM or 64K RAM chip and said second density is normal density, each of said number of blocks of a first of said two boards being coupled to a different one of a first group of said first decoder circuit output terminals and each of said number of blocks of a second of said two boards being coupled to a different one of a second group of said first decoder circuit output terminals, said first decoder circuit being operative in response to successively increasing values of said first and second combinations of address bits to enable for access, storage locations in successive blocks of 256K RAM or 64K RAM chips in said first and then said second memory module boards.

29. The system of claim 27 wherein said number of decoder circuits further includes:

a second decoder circuit having a number of enabling input terminals, a plurality of input select terminals and a plurality of output terminals, said number of enabling input terminals being connected to receive said first one of said identification signals and said input select terminals being selectively connected to receive third and fourth combinations of address bits of said multibit address portion, said second decoder circuit being enabled for operation when said first one of said identification signals is coded to specify said first density and said second decoder circuit when enabled being operative to generate said number of said decode selection signals in said predetermined sequence for successively addressing storage locations within said first or second type of memory chips in each of said number of memory module boards.

30. The system of claim 29 wherein said number of memory module boards is at least two, said first or second type is a 256K RAM or 64K RAM chip and said first density is double density, each of said number of rows of said two boards being coupled to a different one of said second decoder circuit output terminals, said second decoder circuit being operative in response to successively increasing values of said third and fourth combinations of address bits to enable for access storage locations in successive groups of blocks of 256K RAM or 64K RAM chips in said first and second memory module boards.

31. The system of claim 27 wherein said decoder circuit means further includes an address multiplexer circuit having a select input terminal, a number of sets of input terminals and a corresponding number of output terminals, said select input terminal being connected to receive said second one of said identification signals, a first one of each of a first plurality of said number of sets of input terminals being connected to receive said first combination of address bits and a second of each of said plurality of said number of sets of input terminals being connected to receive said second combination of address bits and a first plurality of said output terminals associated with said first plurality of said number of sets of input terminals being connected to said input select terminals of said first decoder circuit, said second one of said identification signals when coded to specify said first type of chip conditioning said multiplexer circuit to apply said first combination of address bits to said first plurality of output terminals and said second one of said identification signals when coded to specify said second type of chip conditioning said multiplexer circuit to apply said second combination of address bits to said first plurality of output terminals.

32. The system of claim 29 wherein said decoder circuit means further includes an address multiplexer circuit having a select input terminal, a number of sets of input terminals and a corresponding number of output terminals, said select input terminal being connected to receive said second one of said identification signals, a first one of each of a second plurality of said number of sets of input terminals being connected to receive said third combination of address bits and a second of each of said second plurality of said number of sets of input terminals being connected to receive said third combination of address bits and a second plurality of said output terminals associated with said second plurality of said number of sets of input terminals being connected to said input select terminals of said second decoder circuit, said second one of said identification signals when coded to specify said first type of chip conditioning said multiplexer circuit to apply said third combination of address bits to said second plurality of output terminals and said second one of said identification signals when coded to specify said second type of chip conditioning said multiplexer circuit to apply said fourth combination of address bits to said second plurality of output terminals.

33. A memory system for accessing data words in response to memory requests, each request having an address coded for specifying a data word to be accessed, said memory system comprising:

a number of identical memory module boards, each including;

a memory section having a number of rows of addressable memory parts, said number of rows and memory parts selected in constructing said memory section defining different characteristics of said memory module board; and

identification section for generating a plurality of identification signals coded for indicating said different characteristics, said identification section of each of said number of boards being connected in common; and

a main board coupled to each of said number of identical memory module boards, said main board including decoder circuit means being coupled to said identification and memory sections of each memory module board and for receiving a predetermined multibit address portion of said address of each request, said decoder circuit means being conditioned by said identification signals for decoding different address bit combinations of said predetermined multibit address portion selected as a function of said coded identification signals to generate said number of said row decode selection signals in a manner for successively addressing of said pluralities of storage locations within each of said rows of said number of identical memory module boards.

34. The system of claim 33 wherein said predetermined multibit address portion corresponds to a number of most significant address bits coded for specifying a maximum number of rows of memory chips includable on said number of identical memory boards installable within said memory system.

35. The system of claim 33 wherein said decoder circuit means includes a plurality of decoder circuits, each of said plurality of said decoder circuits having an enabling input circuit and an input select circuit, said enabling input circuit of each of said plurality of said decoder circuits being coupled to receive at least one of said coded identification signals and said input select circuit of each decoder circuit being coupled to receive at least one of said different address bit combinations of said predetermined multibit address portion, each decoder circuit when enabled by said coded identification signals being operative to generate said row decode selection signals for application to said memory module boards in said predetermined sequence as specified by the coding of said different address bit combination applied to said decoder circuit input select circuit.

36. The system of claim 33 wherein said memory module boards are constructed to have one of a plurality of densities and to have one of a plurality of types of memory chips, said means of said identification section including a plurality of output terminals and a corresponding number of configurable jumper conductor means selectively connected to different ones of said output terminals for generating said coded identification signals.

37. The system of claim 36 wherein a first one of said number of configurable jumper conductor means being selectively connected to a first one of said output terminals for generating a first one of said identification signals coded to specify when said memory section contains first or second types of memory chips in said number of rows;

and

a second one of said number of configurable jumper connector means being selectively connected to a second one of said output terminals for generating a second one of said identification signals coded to specify when said memory module board has a first density or second density of said rows of memory chips.

38. The system of claim 35 wherein said decoder circuit means further includes:

first and second decoder circuits, each having a number of enabling input terminals, a plurality of input select terminals, and a plurality of output terminals, said enabling input terminals of said first and second decoder circuits being connected to receive said first and second ones of said identification signals and said plurality of input select terminals of said first and second decoder circuits being connected to receive first and second combinations of address bits of said multibit address portion, said first decoder circuit being enabled for operation only when said first and second ones of said identification signals are coded to specify that said memory sections of said number of memory module boards have said second density and contain said second type of memory chips and said second decoder circuit being enabled for operation only when said first and second ones of said identification signals are coded to specify that said memory sections of said number of memory module boards have said first density and contain said second type of memory chips and said first and second decoder circuits when enabled being operative to generate said row decode selection signals in said predetermined sequence for successively addressing storage locations within said rows of each of said number of memory module boards.

39. The system of claim 38 wherein said number of memory module boards is two, said second type of chip is a 64K RAM chip and said first and second densities are double and normal densities, each of said number of rows of a first of said two boards being coupled to a different one of a first group of said first decoder circuit output terminals and each of said number of rows of a second of said two boards being coupled to a different one of a second group of said first decoder circuit output terminals and each of said number of rows of said two boards being coupled to different ones of said second and decoder circuit output terminals, said first and second decoder circuits being operative in response to successively increasing values of said first and second combinations of address bits to enable for access locations in successive rows of 64K RAM chips in said first and then said second memory module boards.

40. The system of claim 38 wherein said decoder circuit means further includes:

a third decoder circuit having at least one enabling input terminal, a plurality of input select terminals and a plurality of output terminals, said enabling input terminal being connected to receive said second one of said identification signals and said plurality of input select terminals being connected to receive a third combination of address bits of said multibit address portion, said third decoder circuit being enabled for operation only when said second one of said identification signals is coded to specify that said memory sections of said number of memory module boards contain said first type of memory chips and said third decoder circuit when enabled being operative to generate a portion of said number of said row decode selection signals in said predetermined sequence for successively addressing blocks of storage locations within each of said number of memory module boards.

41. The system of claim 40 wherein said number of memory module boards is one and said first type of chip is a 256K RAM chip, each of said number of rows of said board being coupled to a different one of said third decoder circuit output terminals, said third decoder circuit being operative in response to successively increasing values of said third combination of address bits to enable for access storage locations in successive rows of 256K RAM chips in said memory module board.

42. The system of claim 41 wherein said memory section of said board is fully populated with rows of chips corresponding to said double density.

43. The system of claim 38 wherein said decoder circuit means further comprises first and second decoder circuits having a number of enabling input terminals, a plurality of input select terminals and a plurality of output terminals, said enabling input terminals of said first and second decoder circuits being connected to receive said first one of said identification signals and said input select terminals of said first and second decoder circuits being selectively connected to receive first and second combinations and third and fourth combinations of address bits of said multibit address portion, said first and second decoder circuits, respectively, being enabled for operation when said first one of said identification signals is coded to specify said second and said first densities, said first and second decoder circuits when enabled being operative to generate said row decode selection signals in said predetermined sequence for addressing storage locations within successive rows of first or second types of memory chips in each of said number of memory module boards.

44. The system of claim 43 wherein said decoder circuit means further includes an address multiplexer circuit having a select input terminal, a number of sets of input terminals and a corresponding number of output terminals, said select input terminal being connected to receive said second one of said identification signals, a first one of each of first and second pluralities of said number of sets of input terminals being connected to receive said first and third combinations of address bits, a second of each of said first and second pluralities of said number of sets of input terminals being connected to receive said second and fourth combinations of address bits and first and second pluralities of said output terminals associated with said first and second pluralities of said number of sets of input terminals being connected to said input select terminals of said first and second decoder circuits, said second one of said identification signals when coded to specify said first type of chip conditioning said multiplexer circuit to apply said first and third combinations of address bits to said first and second pluralities of output terminals and said second one of said identification signals when coded to specify said second type of chip conditioning said multiplexer circuit to apply said second and fourth combinations of address bits to said first and second pluralities of output terminals.

45. The system of claim 33 wherein said memory request address further includes row and column address portions, said main board further including an address section comprising:

a plurality of address registers, a first one of said registers being coupled to said decoder circuit means and connected for storing said predetermined multibit address, second and third ones of said registers being coupled to said memory module boards and connected for storing said row and column address portions respectively; and

a multiplexer circuit having a number of input control terminals, a plurality of input terminals and at least one output terminal, said input control terminals being connected to receive said second one of said identification signals and a timing signal coded for indicating the portion of a memory cycle of operation being performed, each of said plurality of input terminals being connected to said first address register for receiving a different predetermined one of said address bits of said predetermined multibit address portion and said number of output terminals being coupled to said memory module boards, said multiplexer circuit being enabled for operation when said second one of said identification signals is coded to specify said first type of chip, and said multiplexer circuit when enabled for operation being conditioned to apply to said output terminal, said different predetermined ones of said address bits during said portion of said memory cycle specified by the coding of said timing signal as the most significant address bits of said row and column address portions applied to said memory module boards by said first and second address registers.

46. The system of claim 45 wherein said main board further includes timing and control circuits, coupled to said address register section and to said memory module boards, said circuits being operative to generate a sequence of timing signals for conditioning said memory module boards for performing a memory cycle of operation in response to said each memory request, a first one of said timing signals being generated at the start of said memory cycle of operation for strobing said row address portion into said memory chips of one of said number of rows of said memory module boards selected by said decoder circuit means and a second one of said timing signals corresponding to said timing signal, said second timing signal being generated subsequent to said start of said memory cycle of operation for conditioning said third address register to apply said column address portion to said memory module boards.

47. The memory system of claim 45 wherein said memory section of each memory board further includes:

a number of jumper conductor means selectively connected to said multiplexer circuit output terminal for receiving said most significant row and column address bits, said number of jumper conductor means being connected to said multiplexer circuit when a first one of said identification signals is coded to specify that said memory section contains said first type of chips and said number of jumper conductor means being disconnected from said multiplexer circuit when said first one of said identification signals is coded to specify that said memory section contains a second type of memory chips.

48. A method of constructing a memory system having a main board and a number of identical memory module boards with different types of memory parts and having different board densities, said method comprising the steps of:

constructing each of said memory module boards to include a memory section and an identification section;

constructing said memory section of each of said memory module boards to accommodate the type of said memory part having the largest number of bit locations;

mounting permanently in said memory section, a number of addressable memory parts of one of said types positioned in blocks so as to provide a given one of said densities;

constructing said identification section for generating identification signals coded for indicating said type of memory part and said board density;

connecting said identification section of each board in common, so as to provide a single set of said coded identification signals;

constructing said main board to include decoder circuit means, having a number of output terminals;

connecting said decoder circuit means to receive a predetermined multibit address portion of the address of each memory request applied to said system and connecting said decoder means to decode different address bit combinations of said predetermined multibit address portion as a function of said coded identification signals and generate a number of row decode selection signals on said output terminals; and

selectively connecting groups of said output terminals to different ones of said memory module boards for enabling the successive addressing of said blocks of said memory parts of said number of boards.

49. A computer memory comprising a plurality of memory module boards connected to a memory control board, wherein said memory control board receives addresses representing a particular storage location of one of said module boards and responds by causing information to be written into or read out therefrom, said memory comprising:

each of said memory module boards including;

a plurality of addressable chip storage units, each of said chip storage units being coupled to receive address signals representing a particular storage location to be accessed;

circuit means for receiving chip storage unit selection denoting signals and for coupling each of said selection denoting signals to a respective one of said chip storage units, each of said selection denoting signals when in a predetermined state enabling the corresponding chip storage unit to perform a cycle of operation upon the addressed storage location; and

,

identification circuit means for delivering identification signals indicating the type of chip storage units and the populated density of said memory module board, and

said common memory control board comprising;

decoding circuit means coupled to receive said identification signals and conditioned to perform a particular decoding function in response to the collective states of said signals; and

,

circuit means adapted to receiving said address signals and to apply a subset of said signals to said decoding circuit, said decoding circuit, as conditioned by said identification signals, decoding said signal subset to deliver to said chip storage unit, said selection denoting signals in which one of said signals is in said predetermined state.