Sense amplifier with time dependent sensitivity

• US 4,545,036 A
• Filed: 10/14/1983
• Issued: 10/01/1985
• Est. Priority Date: 10/14/1983
• Status: Expired due to Term

• Current Assignee: SGS Thomson Microelectronics Inc (STMicroelectronics NV)
• Original Assignee: Mostek Corporation (Rtx Corporation)
• Inventors: Segers, Dennis L.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US06/541,926
• Time in Patent Office: 718 Days
• Field of Search: 365/104, 365/182, 365/189, 365/230, 365/200
• US Class Current: 365/189.09
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 5/005 Circuit means for protection against loss of information of semiconductor storage devices

Abstract

A dynamic RAM integrated circuit has improved resistance to soft errors caused by alpha particles by changing the trip-point voltage of the sense amplifier from a first value that provides resistance to bit line errors to a second, lower value that provides resistance to cell errors.

Claims

1. An integrated circuit memory comprising:

a plurality of memory cells; and

a sense amplifier having first and second inputs, at least one of which is connectable through a bit line to at least one of said plurality of memory cells, for producing an output dependent on an input voltage difference between a cell voltage on that one of said first and second inputs connected to a selected memory cell and a reference trip-point voltage on the other of said first and second inputs;

characterized in that;

said reference trip-point voltage is controlled by time-dependent voltage control means to change over a predetermined time period from a first reference trip-point voltage after equilibration of said first and second inputs to a second reference trip-point voltage.

2. An integrated circuit according to claim 1, in which said first reference trip-point voltage is substantially midway between ground and a supply voltage and said second reference trip-point voltage is closer to ground than said first reference trip-point voltage.

3. An integrated circuit according to claim 2, in which both of said first and second inputs are connectable through at least first and second bit lines to predetermined memory cells, one of said first and second bit lines carrying said cell voltage and the other of said first and second bit lines carrying said reference trip-point voltage.

4. An integrated circuit according to claim 2, in which said reference trip-point voltage is supplied by a dummy memory cell connected to said other of said first and second inputs, said dummy memory cell further comprising a dummy capacitor and means for charging said dummy capacitor to a predetermined dummy reference voltage.