Lateral bidirectional notch FET with extended gate insulator

• US 4,546,367 A
• Filed: 06/21/1982
• Issued: 10/08/1985
• Est. Priority Date: 06/21/1982
• Status: Expired due to Fees

• Current Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Original Assignee: Eaton Corp. (Wisconsin) (Eaton Corporation PLC.)
• Inventors: Benjamin, James A., Schutten, Herman P., Lade, Robert W.
• Primary Examiner(s): Clawson, Jr., Joseph E.
• Application Number:
  US06/390,473
• Time in Patent Office: 1,205 Days
• Field of Search: 357/55, 357/59, 357/86, 357/23.4, 357/23.14
• US Class Current: 257/331
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

Lateral FET structure is disclosed for bidirectional power switching, including AC application. A notch extends downwardly from a top major surface to separate left and right source regions and left and right channel regions, and direct the drift region current path between the channels around the bottom of the notch. Gate electrode means in the notch proximate the channels controls bidirectional conduction.

Claims

1. A bidirectional FET, comprising:

a first source region of one conductivity type semiconductor material;

a first channel region of opposite conductivity type semiconductor material forming a junction with said first source region;

a single drift region of one conductivity type semiconductor material forming another junction with said first channel region;

a second channel region of said opposite conductivity type semiconductor material forming a junction with said drift region;

a second source region of said one conductivity type semiconductor material forming a junction with said second channel region;

a notch extending between and separating said first and second source regions and said first and second channel regions, and extending into said drift region;

insulated gate means in said notch proximate said first and second channel regions and adapted for application of an electrical potential for producing electric fields of sufficient intensity to invert the conductivity type in said first and second channel regions;

whereby upon application of voltage of either polarity to said first and second current source regions, electric current can flow in a respective corresponding direction between them, under control of said electrical potential of said gate means, the conductive current path through said drift region traversing along one side of said notch then around the end thereof then along the other side of said notch;

said single drift region around said notch supporting OFF state blocking voltage in both directions;

wherein said channel regions are laterally sapced by said notch, and said notch extends vertically downwardly from a top major surface of said FET, said channel regions extending generally vertically along respective sides of said notch, said drift region being below said channel regions, two junctions being mesa stacked on each side of said notch, a first side of said notch having said junction between said first source region and said first channel region and said junction between said first channel region and said drift region, a second side of said notch having said junction between said second source region and said second channel region and said junction between said second channel region and said drift region;

wherein said source regions are laterally spaced along said top major surface by said notch therebetween, said source regions being above respective said channel regions;

and comprising a pair of main electrodes each connected to a respective said source region, and wherein said insulated gate means comprises insulation layer means extending along the inner surface of said notch, and gate electrode means disposed in said notch along said insulation layer means such that said gate electrode means extends in close proximity along and insulated from said vertical channel regions;

wherein said FET has an OFF state in the absence of said electric gate potential, with the junction between said drift region and one of said channel regions blocking current flow toward one of said main electrodes, and with the junction between said drift region and the other said channel regions blocking current flow toward the other of said main electrodes;

wherein the drift region current path between said main electrodes extends from said source region downwardly through said channel regions and downwardly around the bottom of said notch so as to increase the drift region current path length and afford higher OFF state blocking voltage capability, without increasing the lateral dimension along said top major surface, whereby to afford a high density, high voltage bidirectional FET structure;

wherein said notch extends downwardly into said drift region a substantial distance below said gate electrode means to substantially diminish attraction of carriers by said gate electrode means from said drift region toward the edges of said notch, to prevent unwanted inducement of conduction channels in said OFF state and afford higher OFF state voltage blocking capability.

2. The invention according to claim 1 wherein said notch extends downwardly into said drift region to a depth substantially below said channel regions, and said gate electrode means extends downwardly to about the depth of said junctions between said channel regions and said drift region.

4. The invention according to claim 2 wherein the portion of said notch below said gate electrode means comprises anodized single crystalline porous silicon oxidized to a substantially insulative condition.

3. Bidirectional laterally integrated power switching plural FET structure comprising:

a semiconductor body having a top major surface and including a lateral substrate layer of one conductivity type at a predetermined depth below said top major surface;

a top layer of opposite conductivity type on said substrate layer;

a plurality of top regions of said one conductivity type formed in said top layer and laterally spaced along said top major surface;

a plurality of notches, each extending downwardly from said top major surface through a respective one of said top regions and through said top layer into said substrate layer, each notch separating its respective said top region into right and left source regions laterally spaced along said top major surface by said notch therebetween, each notch also separating the portion of said top layer below its respective said top region into right and left channel regions below said right and left source regions and likewise laterally spaced by the respective said notch extending therebetween, each notch further providing a singular drift region of said one conductivity type through said substrate layer, which singular drift region extends generally vertically along the sides of said notch and around the bottom thereof to provide substantially increased singular drift region of said one conductivity type length without increased lateral dimension, said singular drift region around said notch supporting OFF state blocking voltage in both directions;

a plurality of first main electrodes connected respectively to said left source regions;

a plurality of second main electrodes connected respectively to said right source regions;

insulated gate electrode means in said notches including portions proximate said right and left channel regions for attracting given polarity carriers to invert said channel regions to said one conductivity type in response to given gate potential, such that current may flow in either direction between said first main electrodes and said second main electrodes, the conductive current path for each FET being from said left source region downwardly through a generally vertical left said channel region along the left side of said notch, then further downwardly into said drift region along said left side of said notch, then around the bottom of said notch in said drift region in said substrate layer, then upwardly along the right side of said notch and said drift region, then upwardly along a generally vertical said right channel region to said right source region, with the same path conducting current in the reverse direction from said right source region to said left source region for each said FET;

wherein said notch extends downwardly into said drift region to a depth substantially below said channel regions, and said gate electrode means extends downwardly to about the depth of the junctions between said channel regions and said drift region, the portion of said notch below said gate electrode means comprising anodized single crystalline porous silicon oxidized to a substantially insulative condition to substantially diminish attraction of carriers by said gate electrode means from said drift region toward the edges of said notch, to prevent unwanted inducement of conduction channels in an OFF state of said FET to increase OFF state voltage blocking capability.

5. A bidirectional lateral power FET, comprising:

a substrate of semiconductor material of one conductivity type having a top major surface;

a pair of channel regions of the other conductivity type laterally spaced in said substrate;

a pair of source regions of said one conductivity type laterally spaced along said top major surface and each forming a junction with a respective one of said channel regions;

a notch in said substrate extending downwardly from said top major surface between said source regions and said channel regions into a drift region in said substrate, such that the conductive current path is directed from one source region downwardly through a generally vertical one said channel region along one side of said notch, then further downwardly into said drift region along said one side of said notch, then around the bottom of said notch, then upwardly along the other side of said notch in said drift region, then upwardly along a generally vertical other said channel region to said other source region, with the same path conducting current in the reverse direction from said other source region to said one source region;

a pair of main electrodes connected respectively to with source regions; and

insulated gate electrode means in said notch including portions proximate said generally vertical channel regions for attracting given polarity carriers to invert said channel regions to said one conductivity type in response to given gate potential, such that current may flow in either direction between said main electrodes;

wherein said notch extends downwardly into said drift region a substantial distance below said gate electrode means to substantially diminish attraction of carriers by said gate electrode means from said drift region toward the edges of said notch, to prevent unwanted inducement of conduction channels in an OFF state of said FET and afford higher OFF state voltage blocking capability.

6. The invention according to claim 5 wherein said notch extends downwardly into said drift region to a depth substantially below said channel regions, and said gate electrode means extends downwardly to about the depth of said channel regions.

7. The invention according to claim 6 wherein the portion of said notch below said gate electrode means comprises anodized single crystalline porous silicon oxidized to a substantially insulative condition.

8. A lateral power FET, comprising:

a substrate of semiconductor material including a lateral n epitaxial layer;

a p type layer on said lateral n epitaxial layer;

an n type region embedded in said p type layer;

a notch extending vertically downwardly through said n type region, through said p type layer, and into said n epitaxial layer to define a vertical plane along mesa stacked said n epitaxial layer, said p type layer and said n type region;

insulated gate means disposed in said notch including portions in close proximity to and insulated from the generally vertical regions in said p type layer on opposite sides of said notch, and adapted for application of electrical gate potential for producing controllable electric fields in said last mentioned vertical regions;

a pair of main electrodes each conductively communicating with a respective one of said embedded n type regions on opposite sides of said notch for serving as an electron current sources when a negative voltage is applied to one of said main electrodes relative to the voltage on the other of said main electrodes, and serving as an anode when a positive voltage is applied to said one main electrode relative to the voltage on said other main electrode;

whereby upon application of voltage of either polarity to said main electrodes, current flow in either direction between said embedded n type regions on opposite sides of said notch is controllable by controlling said potential on said gate means;

wherein the conductive current path through said substrate extends generally vertically along opposite sides of said notch and around the bottom thereof so as to increase the drift region path length through said n epitaxial layer of said FET without increasing the lateral dimension, whereby to afford higher voltage blocking capability in a smaller lateral area;

wherein said notch extends downwardly into said n epitaxial layer a substantial distance below said gate means to substantially diminish attraction of holes by said gate means for said n epitaxial layer toward the edges of said notch, to prevent unwanted inducement of conductive p channels between said p layers on opposite sides of said notch in an OFF state of said FET, to afford increased OFF state voltage blocking capability.

9. The invention according to claim 8 wherein said notch extends dowwardly into said n epitaxial layer to a depth substantially below said p type layers on opposite sides of said notch, and said gate means extends downwardly into said notch to about the depth of the junctions between said p layers and said epitaxial layer.

10. The invention according to claim 9 wherein the portion of said notch below said gate means comprises anodized single crystalline porous silicon oxidized to a substantially insulative condition.