Method of making submicron FET structure

• US 4,546,535 A
• Filed: 12/12/1983
• Issued: 10/15/1985
• Est. Priority Date: 12/12/1983
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Shepard, Joseph F.
• Primary Examiner(s): Ozaki, George T.
• Application Number:
  US06/560,624
• Time in Patent Office: 673 Days
• Field of Search: 29/571, 29/578, 29/591, 148/187, 148/188
• US Class Current: 438/304
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 23/53271 containing semiconductor material, e.g. polysilicon
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66606 with final source and drain contacts formation strictly before final or dummy gate formation, e.g. contact first technology H01L29/66621 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor body having at least a surface region of a first conductivity is provided with a insulating layer over the surface region. A substantially horizontal first conductive layer is formed over the insulating layer. The insulating and first conductive layers are masked and etched to form openings in the layers to the semiconductor body where the source, drain and gate region of the device is desired to be formed. The openings have substantially vertical surfaces on the layered structure. A conformal, highly doped of a second conductivity conductive layer is formed over the openings having these vertical surfaces and over the insulating and conductive layers. The conformal layer is anisotropically etched to substantially remove the horizontal portions of the conformal layer while leaving the openings with a substantially vertical conformal conductive layer on the sides thereof. The body is heated to cause the dopant of a second conductivity to diffuse into the body from the conformal layer to form the source and drain regions and a first insulating layer upon the surface of the first conductive layer and the conformal layer. A second insulating layer is formed over the vertical conformal layer. Then a gate dielectric is formed upon the surface of the semiconductor body between the source and drain regions. Electrical contacts are made to the first conductive layer through the first insulator layer which effectively makes electrical contact to the source and drain regions through the horizontal conductive layer and the vertical conformal conductive layer.

Claims

1. A method of forming a small area field effect transistor device and making contact thereto comprising:

providing a monocrystalline semiconductor body whose at least surface region is of a first conductivity;

forming an insulating layer on said surface region;

forming a substantially horizontal, patterned first conductive layer over said insulating layer;

masking and etching said insulating and first conductive layers to provide an opening in said layers to the semiconductor body where the source, drain and gate regions of said device is desired to be formed;

said opening have substantially vertical surfaces on the layered structure;

forming a conformal highly doped of a second conductivity conductive layer over said openings having said substantially vertical surfaces and over said insulating and patterned conductive layer;

etching said conformal conductive layer to substantially remove the horizontal portions of said conformal layer while leaving said opening with a substantially vertical said conformal conductive layer on the designated sides of said opening;

heating said body and said layered structure at a suitable temperature to cause dopant of a second conductivity to diffuse into said body from said conformal conductive layer to form said source and drain regions and first insulator layer upon the surface of the said first conductive layer and said conformal conductor layer;

forming a second insulator layer over said vertical conformal conductive layer;

forming a gate dielectric on the surface of said semiconductor body between the said source and drain region;

forming a gate conductive layer over said gate dielectric;

forming electrical contacts to said patterned first conductive layer through said first insulator layer which effectively makes electrical contacts to said source and drain regions through said first patterned conductive layer and said vertical conformal conductive layers; and

forming an electrical contact to said gate conductive layer.

2. The method of claim 1 wherein said vertical conformal conductive layers are composed of highly doped polycrystalline silicon, said patterned horizontal conductive layers are composed of a refractory metal, and said semiconductor body is composed of monocrystalline silicon.

3. The method of claim 2 wherein said vertical conformal conductive layers are composed of highly doped polycrystalline silicon, said patterned horizontal conductive layers are composed of a refractory metal silicide, and said semiconductor body is composed of monocrystalline silicon.

4. The method of claim 2 or 3 wherein said semiconductor body is composed of P type monocrystalline silicon and said source and drains are N type.

5. The method of claim 4 wherein after said heating said body the said first insulator layer is also formed upon the exposed monocrystalline layer, and after said heating an ion implantation of N- type ions are made into the horizontal portions of said first insulator layer, removing the second and first insulator layers on the horizontally exposed said semiconductor surface after the forming of said second insulator, and N- lightly doped source and drain regions are formed adjacent and contiguous to said source and drain regions by out-diffusion from the remaining first insulator layer on the said semiconductor surface during the said forming of a gate dielectric.

6. The method of claim 1 wherein the minimum thickness of the said vertical conformal conductors is between about 100 to 500 nanometers and the channel length is less than about 1000 nanometers.